Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1810	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1920	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2005	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1985	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1987	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2134	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1966	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2124	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2086	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1855	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2119	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1978	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1985	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1965	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1962	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2070	0	0
adc_en_ctl_rd_A	2147483647	1530	0	0
adc_fsm_rst_rd_A	2147483647	1646	0	0
adc_intr_ctl_rd_A	2147483647	1774	0	0
adc_lp_sample_ctl_rd_A	2147483647	1613	0	0
adc_pd_ctl_rd_A	2147483647	1789	0	0
adc_sample_ctl_rd_A	2147483647	1464	0	0
adc_wakeup_ctl_rd_A	2147483647	1521	0	0
intr_enable_rd_A	2147483647	2173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1810	0	0
T13	578866	52	0	0
T15	0	39	0	0
T16	0	23	0	0
T17	0	45	0	0
T18	0	38	0	0
T19	0	47	0	0
T20	0	15	0	0
T21	0	24	0	0
T22	0	12	0	0
T23	0	15	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1920	0	0
T13	578866	36	0	0
T15	0	23	0	0
T16	0	31	0	0
T17	0	34	0	0
T18	0	31	0	0
T19	0	38	0	0
T20	0	12	0	0
T21	0	17	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2005	0	0
T13	578866	45	0	0
T15	0	12	0	0
T16	0	27	0	0
T17	0	47	0	0
T18	0	30	0	0
T19	0	31	0	0
T20	0	17	0	0
T21	0	23	0	0
T22	0	6	0	0
T23	0	6	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1985	0	0
T13	578866	40	0	0
T15	0	24	0	0
T16	0	41	0	0
T17	0	27	0	0
T18	0	37	0	0
T19	0	47	0	0
T20	0	11	0	0
T21	0	17	0	0
T22	0	13	0	0
T23	0	7	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1987	0	0
T13	578866	28	0	0
T15	0	19	0	0
T16	0	42	0	0
T17	0	50	0	0
T18	0	42	0	0
T19	0	33	0	0
T20	0	10	0	0
T21	0	15	0	0
T22	0	17	0	0
T23	0	13	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2134	0	0
T13	578866	26	0	0
T15	0	6	0	0
T16	0	45	0	0
T17	0	39	0	0
T18	0	29	0	0
T19	0	57	0	0
T20	0	17	0	0
T21	0	26	0	0
T22	0	6	0	0
T23	0	12	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1966	0	0
T13	578866	26	0	0
T15	0	16	0	0
T16	0	44	0	0
T17	0	29	0	0
T18	0	36	0	0
T19	0	46	0	0
T20	0	26	0	0
T21	0	22	0	0
T22	0	13	0	0
T23	0	11	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2124	0	0
T13	578866	25	0	0
T15	0	35	0	0
T16	0	47	0	0
T17	0	48	0	0
T18	0	37	0	0
T19	0	42	0	0
T20	0	9	0	0
T21	0	8	0	0
T22	0	2	0	0
T23	0	22	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2086	0	0
T13	578866	36	0	0
T15	0	19	0	0
T16	0	35	0	0
T17	0	33	0	0
T18	0	40	0	0
T19	0	39	0	0
T20	0	26	0	0
T21	0	27	0	0
T22	0	13	0	0
T23	0	9	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1855	0	0
T13	578866	35	0	0
T15	0	26	0	0
T16	0	32	0	0
T17	0	24	0	0
T18	0	42	0	0
T19	0	44	0	0
T20	0	24	0	0
T21	0	1	0	0
T22	0	13	0	0
T23	0	19	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2119	0	0
T13	578866	33	0	0
T15	0	27	0	0
T16	0	34	0	0
T17	0	39	0	0
T18	0	46	0	0
T19	0	30	0	0
T20	0	14	0	0
T21	0	27	0	0
T22	0	8	0	0
T23	0	7	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T13	578866	34	0	0
T15	0	11	0	0
T16	0	21	0	0
T17	0	46	0	0
T18	0	36	0	0
T19	0	27	0	0
T20	0	16	0	0
T21	0	5	0	0
T22	0	11	0	0
T23	0	16	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1985	0	0
T13	578866	27	0	0
T15	0	11	0	0
T16	0	33	0	0
T17	0	26	0	0
T18	0	34	0	0
T19	0	45	0	0
T20	0	11	0	0
T21	0	20	0	0
T22	0	17	0	0
T23	0	27	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1965	0	0
T13	578866	28	0	0
T15	0	16	0	0
T16	0	42	0	0
T17	0	30	0	0
T18	0	31	0	0
T19	0	28	0	0
T20	0	14	0	0
T21	0	17	0	0
T22	0	21	0	0
T23	0	6	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1962	0	0
T13	578866	33	0	0
T15	0	14	0	0
T16	0	48	0	0
T17	0	32	0	0
T18	0	36	0	0
T19	0	24	0	0
T20	0	19	0	0
T21	0	17	0	0
T22	0	9	0	0
T23	0	16	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2070	0	0
T13	578866	30	0	0
T15	0	19	0	0
T16	0	32	0	0
T17	0	33	0	0
T18	0	60	0	0
T19	0	52	0	0
T20	0	23	0	0
T21	0	15	0	0
T22	0	19	0	0
T23	0	7	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1530	0	0
T13	578866	40	0	0
T15	0	28	0	0
T16	0	30	0	0
T17	0	46	0	0
T18	0	22	0	0
T19	0	30	0	0
T20	0	11	0	0
T21	0	12	0	0
T22	0	10	0	0
T23	0	14	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1646	0	0
T13	578866	39	0	0
T15	0	15	0	0
T16	0	49	0	0
T17	0	55	0	0
T18	0	21	0	0
T19	0	53	0	0
T20	0	22	0	0
T21	0	34	0	0
T22	0	14	0	0
T23	0	7	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1774	0	0
T13	578866	46	0	0
T15	0	11	0	0
T16	0	37	0	0
T17	0	30	0	0
T18	0	30	0	0
T19	0	33	0	0
T20	0	15	0	0
T21	0	21	0	0
T22	0	15	0	0
T23	0	7	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1613	0	0
T13	578866	30	0	0
T15	0	18	0	0
T16	0	58	0	0
T17	0	38	0	0
T18	0	36	0	0
T19	0	52	0	0
T20	0	16	0	0
T21	0	3	0	0
T22	0	6	0	0
T23	0	2	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1789	0	0
T13	578866	29	0	0
T15	0	17	0	0
T16	0	46	0	0
T17	0	31	0	0
T18	0	48	0	0
T19	0	57	0	0
T20	0	15	0	0
T21	0	13	0	0
T22	0	16	0	0
T23	0	11	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1464	0	0
T13	578866	51	0	0
T15	0	29	0	0
T16	0	25	0	0
T17	0	39	0	0
T18	0	33	0	0
T19	0	36	0	0
T20	0	21	0	0
T21	0	8	0	0
T22	0	17	0	0
T23	0	13	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1521	0	0
T13	578866	25	0	0
T15	0	2	0	0
T16	0	37	0	0
T17	0	38	0	0
T18	0	46	0	0
T19	0	48	0	0
T20	0	29	0	0
T21	0	15	0	0
T22	0	7	0	0
T23	0	12	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2173	0	0
T13	578866	42	0	0
T15	0	25	0	0
T16	0	58	0	0
T17	0	74	0	0
T18	0	76	0	0
T19	0	40	0	0
T20	0	22	0	0
T24	605852	0	0	0
T25	40815	0	0	0
T26	472522	0	0	0
T27	583481	0	0	0
T28	192842	0	0	0
T29	438192	0	0	0
T30	148573	0	0	0
T31	43783	0	0	0
T32	8342	0	0	0
T33	0	7	0	0
T34	0	10	0	0
T35	0	8	0	0