Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205904	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1176072

1

T1

1464

T2

2032

T3

4211

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2085983	1			T1	2547		T2	3896		T3	8184
values[0x0]	147770	1			T1	157		T2	146		T3	217
values[0x1]	148223	1			T1	174		T2	131		T3	267

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	966054	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1415922

1

T1

1779

T2

2452

T3

5101

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7111	1			T1	6		T2	14		T3	19
valid_sources[0x01]	8454	1			T1	7		T2	8		T3	51
valid_sources[0x02]	7108	1			T1	2		T2	30		T3	16
valid_sources[0x03]	7389	1			T1	7		T2	18		T3	64
valid_sources[0x04]	11534	1			T1	7		T2	21		T3	29
valid_sources[0x05]	7211	1			T1	2		T2	5		T3	56
valid_sources[0x06]	6963	1			T1	1		T2	14		T3	16
valid_sources[0x07]	7119	1			T1	4		T2	14		T3	33
valid_sources[0x08]	7998	1			T1	10		T2	22		T3	47
valid_sources[0x09]	7597	1			T1	9		T2	4		T3	27
valid_sources[0x0a]	8007	1			T1	1		T2	4		T3	38
valid_sources[0x0b]	7412	1			T2	25		T3	39		T5	11
valid_sources[0x0c]	8592	1			T2	19		T3	39		T5	9
valid_sources[0x0d]	7084	1			T1	3		T2	5		T3	29
valid_sources[0x0e]	8938	1			T1	4		T2	17		T3	33
valid_sources[0x0f]	13088	1			T1	7		T2	25		T3	28
valid_sources[0x10]	7024	1			T1	2		T2	18		T3	34
valid_sources[0x11]	7119	1			T1	14		T2	18		T3	24
valid_sources[0x12]	11552	1			T1	2		T2	28		T3	34
valid_sources[0x13]	7994	1			T1	4		T2	20		T3	37
valid_sources[0x14]	10533	1			T1	6		T2	18		T3	29
valid_sources[0x15]	12833	1			T1	979		T2	20		T3	30
valid_sources[0x16]	7196	1			T1	8		T2	22		T3	20
valid_sources[0x17]	6860	1			T1	4		T2	12		T3	15
valid_sources[0x18]	8171	1			T1	2		T2	10		T3	32
valid_sources[0x19]	7855	1			T1	2		T2	18		T3	45
valid_sources[0x1a]	7072	1			T1	3		T2	4		T3	32
valid_sources[0x1b]	7304	1			T1	3		T2	8		T3	28
valid_sources[0x1c]	7259	1			T1	6		T2	11		T3	22
valid_sources[0x1d]	15738	1			T1	3		T2	21		T3	49
valid_sources[0x1e]	7367	1			T1	7		T2	21		T3	36
valid_sources[0x1f]	7086	1			T1	4		T2	11		T3	56
valid_sources[0x20]	7086	1			T1	5		T2	15		T3	51
valid_sources[0x21]	26361	1			T1	6		T2	12		T3	35
valid_sources[0x22]	7264	1			T1	8		T2	24		T3	39
valid_sources[0x23]	7030	1			T1	8		T2	17		T3	36
valid_sources[0x24]	11118	1			T1	12		T2	11		T3	34
valid_sources[0x25]	13739	1			T1	11		T2	12		T3	48
valid_sources[0x26]	7155	1			T1	1		T2	25		T3	22
valid_sources[0x27]	8267	1			T1	2		T2	5		T3	31
valid_sources[0x28]	8234	1			T1	6		T2	9		T3	53
valid_sources[0x29]	7027	1			T1	3		T2	16		T3	25
valid_sources[0x2a]	6996	1			T1	8		T2	24		T3	14
valid_sources[0x2b]	9087	1			T1	2		T2	21		T3	56
valid_sources[0x2c]	11723	1			T1	4		T2	5		T3	60
valid_sources[0x2d]	15497	1			T1	5		T2	23		T3	41
valid_sources[0x2e]	8030	1			T1	13		T2	21		T3	39
valid_sources[0x2f]	7488	1			T1	4		T2	15		T3	22
valid_sources[0x30]	7106	1			T1	1		T2	8		T3	48
valid_sources[0x31]	7326	1			T2	25		T3	36		T5	11
valid_sources[0x32]	7310	1			T2	10		T3	31		T5	8
valid_sources[0x33]	7478	1			T1	6		T2	10		T3	50
valid_sources[0x34]	11444	1			T1	3		T2	9		T3	35
valid_sources[0x35]	7229	1			T1	2		T2	14		T3	28
valid_sources[0x36]	9081	1			T1	5		T2	18		T3	11
valid_sources[0x37]	11906	1			T2	14		T3	26		T5	9
valid_sources[0x38]	6943	1			T1	5		T2	15		T3	54
valid_sources[0x39]	8285	1			T1	1		T2	13		T3	39
valid_sources[0x3a]	8101	1			T2	22		T3	42		T4	949
valid_sources[0x3b]	11254	1			T1	3		T2	14		T3	29
valid_sources[0x3c]	7203	1			T1	1		T2	11		T3	38
valid_sources[0x3d]	11665	1			T1	3		T2	19		T3	32
valid_sources[0x3e]	8196	1			T1	4		T2	30		T3	27
valid_sources[0x3f]	11848	1			T2	16		T3	41		T5	13
valid_sources[0x40]	7152	1			T1	6		T2	9		T3	28
valid_sources[0x41]	6977	1			T1	1		T2	14		T3	48
valid_sources[0x42]	7350	1			T1	3		T2	25		T3	21
valid_sources[0x43]	15802	1			T2	10		T3	17		T5	11
valid_sources[0x44]	9995	1			T1	1		T2	19		T3	26
valid_sources[0x45]	12564	1			T2	28		T3	25		T5	9
valid_sources[0x46]	6955	1			T1	4		T2	13		T3	43
valid_sources[0x47]	11297	1			T2	21		T3	44		T5	12
valid_sources[0x48]	14660	1			T1	3		T2	13		T3	34
valid_sources[0x49]	7758	1			T1	2		T2	23		T3	30
valid_sources[0x4a]	7305	1			T1	2		T2	19		T3	56
valid_sources[0x4b]	7633	1			T1	7		T2	22		T3	54
valid_sources[0x4c]	19946	1			T1	2		T2	26		T3	26
valid_sources[0x4d]	10123	1			T2	20		T3	53		T5	7
valid_sources[0x4e]	7324	1			T1	5		T2	15		T3	45
valid_sources[0x4f]	7743	1			T1	4		T2	23		T3	29
valid_sources[0x50]	7255	1			T1	6		T2	16		T3	45
valid_sources[0x51]	7435	1			T1	2		T2	21		T3	24
valid_sources[0x52]	8258	1			T1	4		T2	9		T3	32
valid_sources[0x53]	7927	1			T1	7		T2	32		T3	36
valid_sources[0x54]	7368	1			T1	3		T2	14		T3	18
valid_sources[0x55]	7951	1			T1	3		T2	8		T3	30
valid_sources[0x56]	12886	1			T1	7		T2	8		T3	20
valid_sources[0x57]	11346	1			T1	3		T2	12		T3	34
valid_sources[0x58]	7054	1			T1	9		T2	13		T3	42
valid_sources[0x59]	7118	1			T1	2		T2	24		T3	31
valid_sources[0x5a]	7127	1			T1	8		T2	11		T3	37
valid_sources[0x5b]	7119	1			T1	4		T2	8		T3	41
valid_sources[0x5c]	6889	1			T1	1		T2	15		T3	20
valid_sources[0x5d]	10384	1			T2	15		T3	46		T5	13
valid_sources[0x5e]	6979	1			T1	6		T2	16		T3	26
valid_sources[0x5f]	13821	1			T1	3		T2	10		T3	26
valid_sources[0x60]	8117	1			T1	2		T2	16		T3	44
valid_sources[0x61]	11485	1			T1	8		T2	16		T3	38
valid_sources[0x62]	7137	1			T1	3		T2	23		T3	34
valid_sources[0x63]	7402	1			T1	1		T2	28		T3	39
valid_sources[0x64]	11482	1			T1	3		T2	14		T3	58
valid_sources[0x65]	7077	1			T1	4		T2	10		T3	32
valid_sources[0x66]	12435	1			T1	3		T2	19		T3	40
valid_sources[0x67]	12522	1			T1	6		T2	25		T3	21
valid_sources[0x68]	14504	1			T1	3		T2	12		T3	31
valid_sources[0x69]	10603	1			T1	2		T2	28		T3	34
valid_sources[0x6a]	6903	1			T1	3		T2	27		T3	28
valid_sources[0x6b]	7277	1			T1	3		T2	10		T3	28
valid_sources[0x6c]	6901	1			T1	2		T2	17		T3	36
valid_sources[0x6d]	8114	1			T1	2		T2	14		T3	17
valid_sources[0x6e]	11675	1			T1	9		T2	23		T3	50
valid_sources[0x6f]	8063	1			T1	5		T2	21		T3	42
valid_sources[0x70]	11620	1			T2	5		T3	21		T5	12
valid_sources[0x71]	8880	1			T1	4		T2	17		T3	27
valid_sources[0x72]	11479	1			T2	13		T3	27		T5	14
valid_sources[0x73]	8048	1			T1	3		T2	17		T3	27
valid_sources[0x74]	6895	1			T1	6		T2	14		T3	47
valid_sources[0x75]	26345	1			T1	6		T2	24		T3	45
valid_sources[0x76]	15888	1			T1	2		T2	19		T3	26
valid_sources[0x77]	11504	1			T1	3		T2	17		T3	56
valid_sources[0x78]	11212	1			T1	7		T2	25		T3	46
valid_sources[0x79]	8883	1			T1	4		T2	14		T3	33
valid_sources[0x7a]	7079	1			T1	4		T2	13		T3	33
valid_sources[0x7b]	8200	1			T1	6		T2	14		T3	17
valid_sources[0x7c]	15738	1			T1	17		T2	11		T3	23
valid_sources[0x7d]	7461	1			T1	2		T2	12		T3	42
valid_sources[0x7e]	9147	1			T1	11		T2	16		T3	58
valid_sources[0x7f]	8536	1			T1	5		T2	15		T3	25
valid_sources[0x80]	12857	1			T1	6		T2	12		T3	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1036962

1

T1

1302

T2

1921

T3

4026

values[0x0]

all_enables

biggest_size

80717

1

T1

89

T2

68

T3

102

values[0x1]

all_enables

biggest_size

58393

1

T1

73

T2

43

T3

83