Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29044	1			T1	24		T2	7		T3	14
auto[PWRUP]	113	1			T8	4		T38	4		T210	2
auto[ONEST_0]	65	1			T8	2		T210	4		T211	3
auto[ONEST_021]	20	1			T8	1		T12	1		T212	1
auto[ONEST_1]	79	1			T8	2		T11	1		T39	2
auto[ONEST_DONE]	4	1			T38	1		T42	1		T213	1
auto[LP_0]	109	1			T8	3		T25	2		T11	1
auto[LP_021]	39	1			T25	1		T38	1		T39	2
auto[LP_1]	131	1			T8	2		T25	1		T38	1
auto[LP_EVAL]	57	1			T8	3		T38	1		T31	1
auto[LP_SLP]	505	1			T8	12		T25	5		T11	1
auto[LP_PWRUP]	36	1			T8	1		T38	1		T39	1
auto[NP_0]	165	1			T8	4		T25	2		T11	1
auto[NP_021]	38	1			T210	1		T12	1		T214	1
auto[NP_1]	168	1			T8	4		T25	2		T11	1
auto[NP_EVAL]	34	1			T25	2		T39	1		T210	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T8

1

T40

1

T215

1

min

28529

1

T1

24

T2

7

T3

14

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28534	1			T1	24		T2	7		T3	14
pow[0x1]	6	1			T32	1		T213	1		T16	1
pow[0x2]	20	1			T25	1		T210	1		T211	1
pow[0x3]	38	1			T8	2		T38	1		T12	1
pow[0x4]	67	1			T25	1		T39	1		T210	2
pow[0x5]	121	1			T8	1		T25	3		T38	4
pow[0x6]	256	1			T8	5		T25	3		T11	1
pow[0x7]	498	1			T8	12		T25	3		T11	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

211

1

T8

4

T11

1

T38

3

min

28069

1

T1

24

T2

7

T3

14

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28070	1			T1	24		T2	7		T3	14
pow[0x4]	1	1			T216	1		-	-		-	-
pow[0x6]	2	1			T211	1		T212	1		-	-
pow[0x7]	1	1			T217	1		-	-		-	-
pow[0x8]	5	1			T218	1		T71	1		T219	1
pow[0x9]	11	1			T8	1		T214	1		T220	1
pow[0xa]	17	1			T8	2		T211	2		T214	1
pow[0xb]	43	1			T8	1		T39	2		T31	1
pow[0xc]	55	1			T8	2		T11	1		T38	1
pow[0xd]	146	1			T8	3		T25	5		T38	3
pow[0xe]	298	1			T8	9		T25	2		T38	4
pow[0xf]	587	1			T8	13		T25	7		T11	1