Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2360	1			T8	42		T25	11		T11	5
auto[PWRUP]	116	1			T8	1		T11	1		T38	4
auto[ONEST_0]	79	1			T8	1		T25	1		T11	1
auto[ONEST_021]	15	1			T42	1		T191	1		T13	1
auto[ONEST_1]	87	1			T8	1		T25	2		T38	2
auto[ONEST_DONE]	5	1			T354	1		T355	1		T356	1
auto[LP_0]	114	1			T8	2		T25	2		T11	1
auto[LP_021]	40	1			T8	1		T38	1		T210	1
auto[LP_1]	139	1			T8	2		T25	1		T11	1
auto[LP_EVAL]	63	1			T8	1		T38	2		T39	1
auto[LP_SLP]	545	1			T8	12		T25	7		T11	2
auto[LP_PWRUP]	26	1			T8	1		T211	1		T191	2
auto[NP_0]	236	1			T8	11		T25	3		T11	1
auto[NP_021]	64	1			T8	1		T25	1		T38	2
auto[NP_1]	254	1			T8	3		T25	2		T11	1
auto[NP_EVAL]	40	1			T30	1		T211	1		T13	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T39

1

T191

1

T357

2

min

2045

1

T8

36

T25

8

T11

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2059	1			T8	36		T25	8		T11	10
pow[0x1]	17	1			T210	1		T12	1		T358	2
pow[0x2]	14	1			T8	1		T40	1		T147	1
pow[0x3]	23	1			T8	1		T25	1		T38	1
pow[0x4]	69	1			T8	2		T25	2		T210	1
pow[0x5]	114	1			T8	4		T25	2		T38	1
pow[0x6]	295	1			T8	2		T25	2		T38	4
pow[0x7]	529	1			T8	10		T25	6		T11	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

167

1

T8

3

T11

1

T38

4

min

1456

1

T8

21

T25

4

T11

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1463	1			T8	21		T25	4		T11	7
pow[0x1]	14	1			T14	1		T133	1		T261	1
pow[0x2]	37	1			T12	3		T30	2		T31	3
pow[0x3]	43	1			T13	1		T33	6		T15	3
pow[0x4]	62	1			T8	5		T11	2		T32	4
pow[0x6]	2	1			T357	1		T359	1		-	-
pow[0x7]	1	1			T360	1		-	-		-	-
pow[0x8]	8	1			T357	1		T175	1		T361	1
pow[0x9]	13	1			T8	1		T218	1		T40	1
pow[0xa]	20	1			T8	1		T211	1		T193	1
pow[0xb]	42	1			T8	1		T25	1		T30	1
pow[0xc]	59	1			T8	2		T25	1		T38	1
pow[0xd]	146	1			T8	2		T25	1		T38	1
pow[0xe]	304	1			T8	8		T25	3		T38	2
pow[0xf]	590	1			T8	10		T25	4		T11	1