Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	32165879	32082123	0	0
FsmStateHwReset_A	1218	1218	0	0
FsmStateSwReset_A	32165879	6502	0	0
LpSampleCntHwReset_A	1218	1218	0	0
LpSampleCntSwReset_A	32165879	6502	0	0
NpSampleCntHwReset_A	1218	1218	0	0
NpSampleCntSwReset_A	32165879	6502	0	0
PwrupTimerCntHwReset_A	1218	1218	0	0
PwrupTimerCntSwReset_A	32165879	6502	0	0
WakeupTimerCntHwReset_A	1218	1218	0	0
WakeupTimerCntSwReset_A	32165879	6502	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32165879	32082123	0	0
T1	109076	108986	0	0
T2	31844	31747	0	0
T3	71950	71898	0	0
T4	32908	32821	0	0
T5	109196	109119	0	0
T6	120257	120181	0	0
T7	101047	100964	0	0
T8	137743	136971	0	0
T9	32865	32797	0	0
T10	65629	65568	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218	1218	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	14	14	0	0
T9	1	1	0	0
T10	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32165879	6502	0	0
T1	109076	24	0	0
T2	31844	7	0	0
T3	71950	14	0	0
T4	32908	9	0	0
T5	109196	22	0	0
T6	120257	26	0	0
T7	101047	21	0	0
T8	137743	19	0	0
T9	32865	9	0	0
T10	65629	12	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218	1218	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	14	14	0	0
T9	1	1	0	0
T10	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32165879	6502	0	0
T1	109076	24	0	0
T2	31844	7	0	0
T3	71950	14	0	0
T4	32908	9	0	0
T5	109196	22	0	0
T6	120257	26	0	0
T7	101047	21	0	0
T8	137743	19	0	0
T9	32865	9	0	0
T10	65629	12	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218	1218	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	14	14	0	0
T9	1	1	0	0
T10	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32165879	6502	0	0
T1	109076	24	0	0
T2	31844	7	0	0
T3	71950	14	0	0
T4	32908	9	0	0
T5	109196	22	0	0
T6	120257	26	0	0
T7	101047	21	0	0
T8	137743	19	0	0
T9	32865	9	0	0
T10	65629	12	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218	1218	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	14	14	0	0
T9	1	1	0	0
T10	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32165879	6502	0	0
T1	109076	24	0	0
T2	31844	7	0	0
T3	71950	14	0	0
T4	32908	9	0	0
T5	109196	22	0	0
T6	120257	26	0	0
T7	101047	21	0	0
T8	137743	19	0	0
T9	32865	9	0	0
T10	65629	12	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1218	1218	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	14	14	0	0
T9	1	1	0	0
T10	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32165879	6502	0	0
T1	109076	24	0	0
T2	31844	7	0	0
T3	71950	14	0	0
T4	32908	9	0	0
T5	109196	22	0	0
T6	120257	26	0	0
T7	101047	21	0	0
T8	137743	19	0	0
T9	32865	9	0	0
T10	65629	12	0	0