Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2422	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2139	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2062	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2281	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2304	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2169	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2215	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2433	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2191	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2301	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2263	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2431	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2092	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2240	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2248	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2171	0	0
adc_en_ctl_rd_A	2147483647	1878	0	0
adc_fsm_rst_rd_A	2147483647	1622	0	0
adc_intr_ctl_rd_A	2147483647	2128	0	0
adc_lp_sample_ctl_rd_A	2147483647	1628	0	0
adc_pd_ctl_rd_A	2147483647	1978	0	0
adc_sample_ctl_rd_A	2147483647	1601	0	0
adc_wakeup_ctl_rd_A	2147483647	1885	0	0
intr_enable_rd_A	2147483647	2105	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2422	0	0
T8	112785	12	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	18	0	0
T12	0	53	0	0
T13	0	16	0	0
T14	0	39	0	0
T15	0	22	0	0
T16	0	35	0	0
T17	0	28	0	0
T18	0	20	0	0
T19	0	13	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2139	0	0
T8	112785	17	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	13	0	0
T12	0	38	0	0
T13	0	24	0	0
T14	0	48	0	0
T15	0	25	0	0
T16	0	29	0	0
T17	0	38	0	0
T18	0	7	0	0
T19	0	5	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2062	0	0
T8	112785	26	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	9	0	0
T12	0	44	0	0
T13	0	26	0	0
T14	0	35	0	0
T15	0	22	0	0
T16	0	26	0	0
T17	0	42	0	0
T18	0	9	0	0
T19	0	7	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2281	0	0
T8	112785	21	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	1	0	0
T12	0	47	0	0
T13	0	17	0	0
T14	0	25	0	0
T15	0	22	0	0
T16	0	26	0	0
T17	0	51	0	0
T18	0	14	0	0
T19	0	19	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2304	0	0
T8	112785	11	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	11	0	0
T12	0	46	0	0
T13	0	15	0	0
T14	0	30	0	0
T15	0	19	0	0
T16	0	34	0	0
T17	0	49	0	0
T18	0	20	0	0
T19	0	7	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2169	0	0
T8	112785	22	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	8	0	0
T12	0	37	0	0
T13	0	18	0	0
T14	0	45	0	0
T15	0	29	0	0
T16	0	50	0	0
T17	0	39	0	0
T18	0	10	0	0
T19	0	10	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2215	0	0
T8	112785	15	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	3	0	0
T12	0	39	0	0
T13	0	14	0	0
T14	0	24	0	0
T15	0	13	0	0
T16	0	33	0	0
T17	0	31	0	0
T18	0	21	0	0
T19	0	17	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2433	0	0
T8	112785	2	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	13	0	0
T12	0	21	0	0
T13	0	20	0	0
T14	0	42	0	0
T15	0	20	0	0
T16	0	29	0	0
T17	0	37	0	0
T18	0	14	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0
T27	0	39	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2191	0	0
T8	112785	15	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	5	0	0
T12	0	42	0	0
T13	0	14	0	0
T14	0	38	0	0
T15	0	27	0	0
T16	0	18	0	0
T17	0	35	0	0
T18	0	24	0	0
T19	0	23	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2301	0	0
T8	112785	28	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	14	0	0
T12	0	37	0	0
T13	0	24	0	0
T14	0	32	0	0
T15	0	15	0	0
T16	0	30	0	0
T17	0	32	0	0
T18	0	15	0	0
T19	0	15	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2263	0	0
T8	112785	23	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	5	0	0
T12	0	50	0	0
T13	0	10	0	0
T14	0	42	0	0
T15	0	22	0	0
T16	0	20	0	0
T17	0	37	0	0
T18	0	36	0	0
T19	0	13	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2431	0	0
T8	112785	19	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	10	0	0
T12	0	42	0	0
T13	0	27	0	0
T14	0	35	0	0
T15	0	26	0	0
T16	0	28	0	0
T17	0	53	0	0
T18	0	31	0	0
T19	0	3	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T8	112785	10	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	26	0	0
T12	0	34	0	0
T13	0	22	0	0
T14	0	33	0	0
T15	0	11	0	0
T16	0	20	0	0
T17	0	36	0	0
T18	0	26	0	0
T19	0	9	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2240	0	0
T8	112785	32	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	12	0	0
T12	0	38	0	0
T13	0	28	0	0
T14	0	46	0	0
T15	0	40	0	0
T16	0	24	0	0
T17	0	34	0	0
T18	0	17	0	0
T19	0	12	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2248	0	0
T8	112785	21	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	16	0	0
T12	0	35	0	0
T13	0	17	0	0
T14	0	28	0	0
T15	0	19	0	0
T16	0	28	0	0
T17	0	30	0	0
T18	0	26	0	0
T19	0	15	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2171	0	0
T8	112785	23	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	7	0	0
T12	0	49	0	0
T13	0	15	0	0
T14	0	44	0	0
T15	0	26	0	0
T16	0	37	0	0
T17	0	48	0	0
T18	0	31	0	0
T19	0	3	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1878	0	0
T8	112785	28	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	9	0	0
T12	0	49	0	0
T13	0	14	0	0
T14	0	36	0	0
T15	0	30	0	0
T16	0	17	0	0
T17	0	26	0	0
T18	0	9	0	0
T19	0	11	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1622	0	0
T8	112785	10	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	16	0	0
T12	0	45	0	0
T13	0	19	0	0
T14	0	30	0	0
T15	0	21	0	0
T16	0	23	0	0
T17	0	32	0	0
T18	0	17	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0
T27	0	50	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2128	0	0
T8	112785	14	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	11	0	0
T12	0	45	0	0
T13	0	10	0	0
T14	0	33	0	0
T15	0	20	0	0
T16	0	40	0	0
T17	0	26	0	0
T18	0	17	0	0
T19	0	21	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1628	0	0
T8	112785	36	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	3	0	0
T12	0	38	0	0
T13	0	25	0	0
T14	0	49	0	0
T15	0	16	0	0
T16	0	31	0	0
T17	0	34	0	0
T18	0	19	0	0
T19	0	1	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T8	112785	16	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	7	0	0
T12	0	49	0	0
T13	0	5	0	0
T14	0	26	0	0
T15	0	19	0	0
T16	0	28	0	0
T17	0	22	0	0
T18	0	21	0	0
T19	0	7	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1601	0	0
T8	112785	20	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	11	0	0
T12	0	47	0	0
T13	0	12	0	0
T14	0	45	0	0
T15	0	6	0	0
T16	0	27	0	0
T17	0	32	0	0
T18	0	19	0	0
T19	0	21	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1885	0	0
T8	112785	22	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	10	0	0
T12	0	43	0	0
T13	0	28	0	0
T14	0	39	0	0
T15	0	19	0	0
T16	0	16	0	0
T17	0	48	0	0
T18	0	18	0	0
T19	0	22	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T8	112785	43	0	0
T9	161047	0	0	0
T10	787563	0	0	0
T11	0	15	0	0
T12	0	53	0	0
T13	0	22	0	0
T14	0	16	0	0
T15	0	18	0	0
T16	0	48	0	0
T17	0	86	0	0
T20	164749	0	0	0
T21	154125	0	0	0
T22	128178	0	0	0
T23	158319	0	0	0
T24	12126	0	0	0
T25	767135	0	0	0
T26	158144	0	0	0
T28	0	18	0	0
T29	0	12	0	0