Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1182990	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1159628

1

T1

2184

T2

4313

T4

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2040568	1			T1	4105		T2	8066		T4	1
values[0x0]	150538	1			T1	110		T2	256		T4	11
values[0x1]	151512	1			T1	117		T2	268		T4	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	947835	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1394783

1

T1

2630

T2

5158

T4

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7083	1			T2	31		T7	41		T9	13
valid_sources[0x01]	11729	1			T2	41		T3	3		T7	60
valid_sources[0x02]	11895	1			T2	19		T3	3		T7	16
valid_sources[0x03]	10518	1			T2	36		T4	1		T3	1
valid_sources[0x04]	14468	1			T2	32		T3	4		T7	45
valid_sources[0x05]	11666	1			T2	41		T3	3		T7	34
valid_sources[0x06]	6791	1			T2	39		T3	2		T7	11
valid_sources[0x07]	7397	1			T2	36		T3	7		T7	30
valid_sources[0x08]	6913	1			T2	34		T3	3		T7	16
valid_sources[0x09]	8153	1			T2	36		T3	11		T7	27
valid_sources[0x0a]	20415	1			T2	35		T3	2		T7	41
valid_sources[0x0b]	8458	1			T2	35		T3	118		T7	33
valid_sources[0x0c]	7879	1			T2	30		T4	4		T3	5
valid_sources[0x0d]	7052	1			T2	30		T3	5		T7	57
valid_sources[0x0e]	7202	1			T2	37		T3	5		T7	19
valid_sources[0x0f]	12157	1			T2	49		T3	4		T7	20
valid_sources[0x10]	8193	1			T2	32		T3	5		T7	84
valid_sources[0x11]	12388	1			T2	22		T3	2		T7	45
valid_sources[0x12]	11887	1			T2	32		T3	2		T7	61
valid_sources[0x13]	15681	1			T2	31		T3	1		T7	24
valid_sources[0x14]	10191	1			T2	24		T3	2		T5	40
valid_sources[0x15]	7313	1			T2	34		T3	6		T5	22
valid_sources[0x16]	24169	1			T2	46		T3	3		T7	20
valid_sources[0x17]	9383	1			T2	44		T3	8		T7	27
valid_sources[0x18]	9238	1			T2	27		T3	7		T5	59
valid_sources[0x19]	7347	1			T2	22		T3	3		T7	21
valid_sources[0x1a]	11653	1			T2	38		T3	1		T7	16
valid_sources[0x1b]	11684	1			T2	21		T3	1		T7	65
valid_sources[0x1c]	6994	1			T2	25		T3	3		T5	57
valid_sources[0x1d]	12160	1			T2	30		T3	93		T7	13
valid_sources[0x1e]	7482	1			T2	33		T3	3		T7	41
valid_sources[0x1f]	7046	1			T2	36		T5	2		T7	28
valid_sources[0x20]	8086	1			T2	41		T3	17		T7	27
valid_sources[0x21]	7296	1			T2	26		T3	5		T7	22
valid_sources[0x22]	7060	1			T2	24		T3	2		T7	23
valid_sources[0x23]	8992	1			T2	30		T3	5		T7	18
valid_sources[0x24]	13508	1			T2	38		T3	6		T7	69
valid_sources[0x25]	6838	1			T2	54		T3	1		T7	19
valid_sources[0x26]	7098	1			T2	32		T3	2		T7	20
valid_sources[0x27]	11796	1			T2	29		T3	3		T7	50
valid_sources[0x28]	7160	1			T2	30		T3	4		T7	59
valid_sources[0x29]	6896	1			T2	24		T3	2		T5	24
valid_sources[0x2a]	7780	1			T2	27		T3	3		T7	36
valid_sources[0x2b]	8095	1			T2	17		T3	5		T5	8
valid_sources[0x2c]	8817	1			T2	45		T3	5		T7	33
valid_sources[0x2d]	7897	1			T2	25		T3	1		T7	37
valid_sources[0x2e]	7093	1			T2	36		T7	31		T9	14
valid_sources[0x2f]	7355	1			T2	24		T3	4		T7	32
valid_sources[0x30]	10804	1			T2	33		T3	87		T7	26
valid_sources[0x31]	11097	1			T2	32		T3	5		T7	74
valid_sources[0x32]	7425	1			T2	41		T3	2		T7	20
valid_sources[0x33]	7036	1			T2	24		T3	3		T5	11
valid_sources[0x34]	7041	1			T2	27		T3	3		T7	17
valid_sources[0x35]	7284	1			T2	24		T3	6		T7	37
valid_sources[0x36]	7251	1			T2	22		T3	4		T5	54
valid_sources[0x37]	6908	1			T2	22		T3	4		T7	29
valid_sources[0x38]	7649	1			T2	36		T4	4		T3	4
valid_sources[0x39]	7166	1			T2	39		T3	4		T7	29
valid_sources[0x3a]	7295	1			T2	33		T3	5		T7	37
valid_sources[0x3b]	9031	1			T2	31		T3	4		T7	28
valid_sources[0x3c]	10348	1			T2	49		T3	5		T7	19
valid_sources[0x3d]	6967	1			T2	29		T3	3		T7	42
valid_sources[0x3e]	7024	1			T2	25		T3	10		T7	40
valid_sources[0x3f]	8212	1			T2	30		T3	1		T7	31
valid_sources[0x40]	11570	1			T2	29		T3	3		T7	45
valid_sources[0x41]	8603	1			T2	47		T3	5		T7	18
valid_sources[0x42]	7232	1			T2	35		T3	5		T5	7
valid_sources[0x43]	7101	1			T2	27		T3	11		T7	20
valid_sources[0x44]	7380	1			T2	25		T3	2		T7	24
valid_sources[0x45]	9388	1			T2	28		T3	3		T7	15
valid_sources[0x46]	7039	1			T2	21		T3	5		T7	17
valid_sources[0x47]	7080	1			T2	21		T7	20		T9	9
valid_sources[0x48]	13512	1			T2	34		T3	181		T5	49
valid_sources[0x49]	7586	1			T2	31		T3	130		T7	68
valid_sources[0x4a]	10681	1			T2	36		T3	5		T7	37
valid_sources[0x4b]	13889	1			T2	42		T3	3		T7	18
valid_sources[0x4c]	7114	1			T2	24		T3	3		T5	10
valid_sources[0x4d]	12794	1			T2	23		T3	1		T7	35
valid_sources[0x4e]	7123	1			T2	25		T3	3		T7	56
valid_sources[0x4f]	7515	1			T2	17		T3	4		T7	33
valid_sources[0x50]	7806	1			T2	34		T3	5		T5	30
valid_sources[0x51]	7272	1			T2	30		T3	2		T7	77
valid_sources[0x52]	7712	1			T2	57		T3	4		T7	20
valid_sources[0x53]	7173	1			T2	48		T3	2		T7	29
valid_sources[0x54]	11775	1			T2	29		T3	5		T7	49
valid_sources[0x55]	13092	1			T2	33		T3	5		T5	27
valid_sources[0x56]	12518	1			T2	30		T3	1		T7	31
valid_sources[0x57]	8396	1			T2	62		T3	4		T5	29
valid_sources[0x58]	10028	1			T2	27		T3	7		T7	18
valid_sources[0x59]	11899	1			T2	42		T3	8		T7	38
valid_sources[0x5a]	11490	1			T2	29		T3	12		T7	37
valid_sources[0x5b]	13302	1			T2	36		T3	4		T5	3
valid_sources[0x5c]	9537	1			T2	29		T3	3		T5	10
valid_sources[0x5d]	7482	1			T2	26		T7	34		T9	9
valid_sources[0x5e]	11367	1			T2	29		T3	3		T7	17
valid_sources[0x5f]	7202	1			T2	64		T3	2		T5	11
valid_sources[0x60]	7229	1			T2	25		T7	26		T9	7
valid_sources[0x61]	9995	1			T2	32		T3	2		T7	17
valid_sources[0x62]	7790	1			T2	30		T3	5		T7	40
valid_sources[0x63]	10720	1			T2	19		T3	2		T7	10
valid_sources[0x64]	11215	1			T2	32		T3	35		T7	24
valid_sources[0x65]	11725	1			T2	40		T3	2		T5	15
valid_sources[0x66]	7163	1			T2	33		T3	5		T7	59
valid_sources[0x67]	7804	1			T2	30		T3	3		T7	30
valid_sources[0x68]	7251	1			T2	46		T3	8		T7	20
valid_sources[0x69]	10548	1			T2	35		T3	5		T7	17
valid_sources[0x6a]	7812	1			T2	42		T3	4		T7	29
valid_sources[0x6b]	9366	1			T2	39		T3	5		T7	50
valid_sources[0x6c]	7220	1			T2	30		T3	3		T7	25
valid_sources[0x6d]	6989	1			T2	38		T4	3		T3	1
valid_sources[0x6e]	7282	1			T2	35		T3	5		T7	16
valid_sources[0x6f]	7616	1			T2	28		T3	7		T5	5
valid_sources[0x70]	8058	1			T2	30		T3	2		T7	41
valid_sources[0x71]	9097	1			T2	28		T7	35		T9	9
valid_sources[0x72]	11917	1			T2	29		T3	3		T7	34
valid_sources[0x73]	13303	1			T2	41		T3	4		T7	18
valid_sources[0x74]	7138	1			T2	34		T3	3		T7	23
valid_sources[0x75]	13431	1			T2	31		T3	152		T7	50
valid_sources[0x76]	11629	1			T2	37		T3	7		T7	50
valid_sources[0x77]	7245	1			T2	24		T3	2		T7	13
valid_sources[0x78]	9876	1			T2	39		T3	2		T7	31
valid_sources[0x79]	6977	1			T2	33		T3	5		T7	50
valid_sources[0x7a]	10892	1			T2	25		T3	2		T7	21
valid_sources[0x7b]	10001	1			T2	26		T3	5		T7	24
valid_sources[0x7c]	8161	1			T2	28		T3	4		T7	53
valid_sources[0x7d]	6903	1			T2	33		T3	4		T7	23
valid_sources[0x7e]	6883	1			T2	30		T3	3		T7	31
valid_sources[0x7f]	7292	1			T2	30		T3	3		T7	24
valid_sources[0x80]	7549	1			T2	56		T3	2		T7	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1016130

1

T1

2092

T2

4100

T4

1

values[0x0]

all_enables

biggest_size

82949

1

T1

49

T2

127

T4

5

values[0x1]

all_enables

biggest_size

60549

1

T1

43

T2

86

T3

43