Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30163	1			T1	4		T2	17		T3	13
auto[PWRUP]	131	1			T5	1		T13	1		T63	1
auto[ONEST_0]	70	1			T59	1		T63	1		T64	1
auto[ONEST_021]	12	1			T63	1		T52	1		T348	1
auto[ONEST_1]	87	1			T5	1		T13	1		T59	3
auto[ONEST_DONE]	7	1			T349	1		T350	1		T351	2
auto[LP_0]	131	1			T13	1		T59	1		T64	2
auto[LP_021]	31	1			T5	1		T63	1		T66	1
auto[LP_1]	139	1			T5	2		T59	1		T63	4
auto[LP_EVAL]	60	1			T13	1		T66	2		T37	2
auto[LP_SLP]	522	1			T5	8		T13	1		T59	3
auto[LP_PWRUP]	21	1			T37	3		T65	1		T170	2
auto[NP_0]	166	1			T5	3		T13	1		T59	1
auto[NP_021]	32	1			T65	1		T170	2		T50	1
auto[NP_1]	172	1			T5	2		T13	1		T63	1
auto[NP_EVAL]	39	1			T5	1		T63	1		T37	2
auto[NP_DONE]	1	1			T50	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T5

1

T37

1

T352

1

min

29610

1

T1

4

T2

17

T3

13

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29619	1			T1	4		T2	17		T3	13
pow[0x1]	8	1			T64	1		T65	1		T117	1
pow[0x2]	11	1			T128	1		T353	1		T354	1
pow[0x3]	32	1			T13	1		T63	1		T66	1
pow[0x4]	73	1			T13	1		T59	1		T66	1
pow[0x5]	144	1			T5	1		T59	2		T63	1
pow[0x6]	297	1			T5	2		T59	2		T63	7
pow[0x7]	533	1			T5	7		T13	1		T59	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

217

1

T5

1

T13

1

T59

5

min

29138

1

T1

4

T2

17

T3

13

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29138	1			T1	4		T2	17		T3	13
pow[0x3]	1	1			T249	1		-	-		-	-
pow[0x4]	1	1			T348	1		-	-		-	-
pow[0x5]	3	1			T32	1		T355	1		T356	1
pow[0x6]	1	1			T357	1		-	-		-	-
pow[0x7]	2	1			T18	1		T358	1		-	-
pow[0x8]	7	1			T117	1		T352	2		T319	1
pow[0x9]	9	1			T64	1		T128	1		T133	1
pow[0xa]	18	1			T5	1		T59	1		T63	1
pow[0xb]	38	1			T63	1		T37	1		T359	1
pow[0xc]	60	1			T59	1		T45	1		T37	3
pow[0xd]	173	1			T5	5		T59	2		T63	1
pow[0xe]	298	1			T5	3		T59	4		T63	2
pow[0xf]	594	1			T5	4		T13	2		T59	3