Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2341	1			T5	21		T11	16		T13	16
auto[PWRUP]	147	1			T13	2		T59	3		T63	2
auto[ONEST_0]	72	1			T5	3		T13	1		T59	1
auto[ONEST_021]	18	1			T37	1		T360	1		T231	1
auto[ONEST_1]	97	1			T5	1		T63	2		T66	1
auto[ONEST_DONE]	4	1			T114	1		T352	1		T361	1
auto[LP_0]	140	1			T5	3		T13	3		T59	1
auto[LP_021]	40	1			T11	1		T64	2		T66	1
auto[LP_1]	147	1			T13	1		T59	2		T63	1
auto[LP_EVAL]	58	1			T5	1		T59	1		T64	1
auto[LP_SLP]	591	1			T5	4		T11	2		T59	2
auto[LP_PWRUP]	27	1			T11	1		T63	2		T64	1
auto[NP_0]	220	1			T5	2		T59	4		T63	1
auto[NP_021]	55	1			T5	2		T59	1		T65	2
auto[NP_1]	246	1			T13	1		T63	1		T64	3
auto[NP_EVAL]	32	1			T5	1		T11	1		T63	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T66

1

T45

1

T67

1

min

2026

1

T5

5

T11

19

T13

18

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2035	1			T5	6		T11	19		T13	18
pow[0x1]	8	1			T37	1		T51	1		T244	1
pow[0x2]	25	1			T45	1		T170	1		T50	1
pow[0x3]	49	1			T11	1		T59	1		T66	1
pow[0x4]	71	1			T5	2		T59	1		T64	1
pow[0x5]	141	1			T5	3		T13	2		T63	1
pow[0x6]	260	1			T5	2		T13	2		T59	4
pow[0x7]	562	1			T5	10		T11	1		T59	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

195

1

T13

2

T59

3

T63

1

min

1314

1

T5

2

T11

19

T13

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1317	1			T5	2		T11	19		T13	15
pow[0x1]	22	1			T48	2		T51	1		T175	1
pow[0x2]	30	1			T13	1		T50	5		T15	4
pow[0x3]	37	1			T11	1		T50	1		T33	1
pow[0x4]	65	1			T32	2		T33	2		T51	2
pow[0x5]	1	1			T362	1		-	-		-	-
pow[0x7]	4	1			T128	1		T363	1		T364	1
pow[0x8]	8	1			T32	1		T363	2		T365	1
pow[0x9]	10	1			T65	1		T354	1		T246	1
pow[0xa]	23	1			T5	1		T63	1		T50	1
pow[0xb]	38	1			T63	1		T64	1		T45	1
pow[0xc]	84	1			T5	3		T59	2		T63	1
pow[0xd]	166	1			T5	1		T59	4		T63	2
pow[0xe]	325	1			T5	2		T59	2		T63	5
pow[0xf]	657	1			T5	9		T13	3		T59	6