Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1538	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1486	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1480	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1625	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1408	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1579	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1483	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1533	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1414	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1549	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1585	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1594	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1469	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1590	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1530	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1722	0	0
adc_en_ctl_rd_A	2147483647	1472	0	0
adc_fsm_rst_rd_A	2147483647	1259	0	0
adc_intr_ctl_rd_A	2147483647	1413	0	0
adc_lp_sample_ctl_rd_A	2147483647	1237	0	0
adc_pd_ctl_rd_A	2147483647	1420	0	0
adc_sample_ctl_rd_A	2147483647	1340	0	0
adc_wakeup_ctl_rd_A	2147483647	1313	0	0
intr_enable_rd_A	2147483647	1802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1538	0	0
T15	465759	23	0	0
T16	0	17	0	0
T17	0	19	0	0
T18	0	13	0	0
T19	0	19	0	0
T20	0	2	0	0
T21	0	41	0	0
T22	0	39	0	0
T23	0	41	0	0
T24	0	29	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1486	0	0
T15	465759	21	0	0
T16	0	26	0	0
T17	0	11	0	0
T18	0	28	0	0
T19	0	8	0	0
T20	0	12	0	0
T21	0	20	0	0
T22	0	33	0	0
T23	0	32	0	0
T24	0	14	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1480	0	0
T15	465759	7	0	0
T16	0	13	0	0
T17	0	12	0	0
T18	0	18	0	0
T19	0	12	0	0
T20	0	5	0	0
T21	0	25	0	0
T22	0	43	0	0
T23	0	42	0	0
T24	0	26	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1625	0	0
T15	465759	21	0	0
T16	0	10	0	0
T17	0	4	0	0
T18	0	25	0	0
T19	0	22	0	0
T20	0	13	0	0
T21	0	28	0	0
T22	0	34	0	0
T23	0	33	0	0
T24	0	33	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1408	0	0
T15	465759	16	0	0
T16	0	11	0	0
T17	0	15	0	0
T18	0	18	0	0
T19	0	30	0	0
T20	0	9	0	0
T21	0	18	0	0
T22	0	50	0	0
T23	0	44	0	0
T24	0	11	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1579	0	0
T15	465759	16	0	0
T16	0	26	0	0
T17	0	2	0	0
T18	0	18	0	0
T19	0	15	0	0
T20	0	12	0	0
T21	0	48	0	0
T22	0	40	0	0
T23	0	27	0	0
T24	0	19	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1483	0	0
T15	465759	25	0	0
T17	0	6	0	0
T18	0	26	0	0
T19	0	29	0	0
T20	0	6	0	0
T21	0	32	0	0
T22	0	18	0	0
T23	0	40	0	0
T24	0	12	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0
T34	0	49	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1533	0	0
T15	465759	27	0	0
T16	0	13	0	0
T17	0	4	0	0
T18	0	28	0	0
T19	0	13	0	0
T20	0	10	0	0
T21	0	22	0	0
T22	0	38	0	0
T23	0	35	0	0
T24	0	27	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1414	0	0
T15	465759	24	0	0
T16	0	10	0	0
T17	0	7	0	0
T18	0	16	0	0
T19	0	36	0	0
T20	0	5	0	0
T21	0	25	0	0
T22	0	50	0	0
T23	0	31	0	0
T24	0	10	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1549	0	0
T15	465759	19	0	0
T16	0	8	0	0
T17	0	2	0	0
T18	0	13	0	0
T19	0	21	0	0
T20	0	13	0	0
T21	0	31	0	0
T22	0	33	0	0
T23	0	32	0	0
T24	0	14	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1585	0	0
T15	465759	9	0	0
T16	0	10	0	0
T17	0	6	0	0
T18	0	9	0	0
T19	0	9	0	0
T20	0	2	0	0
T21	0	51	0	0
T22	0	44	0	0
T23	0	56	0	0
T24	0	24	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1594	0	0
T15	465759	24	0	0
T16	0	15	0	0
T17	0	8	0	0
T18	0	23	0	0
T19	0	24	0	0
T20	0	4	0	0
T21	0	39	0	0
T22	0	42	0	0
T23	0	39	0	0
T24	0	21	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1469	0	0
T15	465759	13	0	0
T16	0	9	0	0
T17	0	10	0	0
T18	0	21	0	0
T19	0	20	0	0
T20	0	7	0	0
T21	0	37	0	0
T22	0	33	0	0
T23	0	25	0	0
T24	0	16	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1590	0	0
T15	465759	21	0	0
T16	0	17	0	0
T17	0	16	0	0
T18	0	20	0	0
T19	0	15	0	0
T20	0	23	0	0
T21	0	30	0	0
T22	0	38	0	0
T23	0	46	0	0
T24	0	9	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1530	0	0
T15	465759	17	0	0
T16	0	22	0	0
T17	0	12	0	0
T18	0	19	0	0
T19	0	27	0	0
T20	0	19	0	0
T21	0	29	0	0
T22	0	34	0	0
T23	0	34	0	0
T24	0	12	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1722	0	0
T15	465759	13	0	0
T16	0	11	0	0
T17	0	4	0	0
T18	0	20	0	0
T19	0	31	0	0
T20	0	18	0	0
T21	0	29	0	0
T22	0	41	0	0
T23	0	39	0	0
T24	0	20	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1472	0	0
T15	465759	17	0	0
T16	0	10	0	0
T17	0	6	0	0
T18	0	18	0	0
T19	0	25	0	0
T20	0	7	0	0
T21	0	40	0	0
T22	0	40	0	0
T23	0	34	0	0
T24	0	16	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1259	0	0
T15	465759	12	0	0
T17	0	6	0	0
T18	0	12	0	0
T19	0	20	0	0
T21	0	48	0	0
T22	0	41	0	0
T23	0	30	0	0
T24	0	19	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0
T34	0	40	0	0
T35	0	22	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1413	0	0
T15	465759	11	0	0
T16	0	15	0	0
T17	0	11	0	0
T18	0	15	0	0
T19	0	27	0	0
T20	0	6	0	0
T21	0	34	0	0
T22	0	39	0	0
T23	0	42	0	0
T24	0	10	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1237	0	0
T15	465759	28	0	0
T16	0	7	0	0
T17	0	8	0	0
T18	0	43	0	0
T19	0	9	0	0
T20	0	1	0	0
T21	0	25	0	0
T22	0	35	0	0
T23	0	33	0	0
T24	0	11	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1420	0	0
T15	465759	10	0	0
T16	0	5	0	0
T17	0	12	0	0
T18	0	23	0	0
T19	0	8	0	0
T20	0	6	0	0
T21	0	37	0	0
T22	0	38	0	0
T23	0	26	0	0
T24	0	24	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1340	0	0
T15	465759	21	0	0
T16	0	8	0	0
T17	0	2	0	0
T18	0	18	0	0
T19	0	37	0	0
T20	0	8	0	0
T21	0	35	0	0
T22	0	28	0	0
T23	0	34	0	0
T24	0	18	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1313	0	0
T15	465759	28	0	0
T16	0	7	0	0
T17	0	13	0	0
T18	0	25	0	0
T19	0	25	0	0
T20	0	3	0	0
T21	0	35	0	0
T22	0	40	0	0
T23	0	43	0	0
T24	0	14	0	0
T25	839557	0	0	0
T26	144784	0	0	0
T27	69926	0	0	0
T28	381754	0	0	0
T29	376692	0	0	0
T30	20801	0	0	0
T31	596555	0	0	0
T32	303590	0	0	0
T33	557567	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1802	0	0
T15	0	54	0	0
T17	0	9	0	0
T18	0	20	0	0
T19	0	8	0	0
T20	0	8	0	0
T21	0	70	0	0
T36	141778	2	0	0
T37	176526	22	0	0
T38	0	5	0	0
T39	0	23	0	0
T40	140679	0	0	0
T41	828995	0	0	0
T42	293138	0	0	0
T43	374417	0	0	0
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