Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1180699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1155142

1

T1

14

T2

61

T3

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2036854	1			T2	81		T4	821		T5	589
values[0x0]	148782	1			T1	18		T2	32		T3	27
values[0x1]	150205	1			T1	13		T2	31		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	945585	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1390256

1

T1

16

T2

77

T3

31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12256	1			T1	1		T3	2		T4	2
valid_sources[0x01]	14251	1			T6	11		T7	26		T8	13
valid_sources[0x02]	11197	1			T4	3		T6	9		T7	15
valid_sources[0x03]	7343	1			T4	4		T6	10		T7	25
valid_sources[0x04]	7293	1			T4	8		T6	8		T7	23
valid_sources[0x05]	6592	1			T1	2		T4	1		T6	3
valid_sources[0x06]	7983	1			T4	1		T6	6		T7	25
valid_sources[0x07]	6658	1			T4	2		T6	42		T7	174
valid_sources[0x08]	7295	1			T4	5		T6	10		T7	19
valid_sources[0x09]	15232	1			T4	12		T7	15		T8	25
valid_sources[0x0a]	7685	1			T5	445		T6	6		T7	14
valid_sources[0x0b]	9916	1			T6	5		T7	70		T9	1
valid_sources[0x0c]	6729	1			T1	3		T6	14		T7	23
valid_sources[0x0d]	6928	1			T4	4		T6	12		T7	16
valid_sources[0x0e]	10972	1			T4	13		T6	7		T7	18
valid_sources[0x0f]	7077	1			T3	1		T4	12		T6	7
valid_sources[0x10]	8145	1			T5	49		T6	3		T7	23
valid_sources[0x11]	6860	1			T1	1		T4	2		T6	18
valid_sources[0x12]	8048	1			T4	5		T6	12		T7	5
valid_sources[0x13]	6938	1			T4	6		T6	6		T7	24
valid_sources[0x14]	6940	1			T4	8		T6	7		T7	33
valid_sources[0x15]	7304	1			T3	2		T4	5		T6	32
valid_sources[0x16]	6765	1			T4	4		T6	5		T7	17
valid_sources[0x17]	7063	1			T4	2		T6	1		T7	23
valid_sources[0x18]	8632	1			T6	36		T7	13		T9	1
valid_sources[0x19]	7360	1			T4	11		T6	14		T7	13
valid_sources[0x1a]	7069	1			T4	4		T7	18		T9	3
valid_sources[0x1b]	7443	1			T3	2		T4	11		T6	4
valid_sources[0x1c]	10225	1			T4	3		T6	8		T7	17
valid_sources[0x1d]	6745	1			T4	3		T6	13		T7	19
valid_sources[0x1e]	8028	1			T4	5		T6	12		T7	23
valid_sources[0x1f]	6850	1			T6	10		T7	15		T9	7
valid_sources[0x20]	10293	1			T6	1		T7	21		T9	4
valid_sources[0x21]	7723	1			T2	18		T6	13		T7	17
valid_sources[0x22]	7051	1			T4	3		T6	16		T7	16
valid_sources[0x23]	11183	1			T6	14		T7	20		T9	3
valid_sources[0x24]	7451	1			T4	2		T6	15		T7	21
valid_sources[0x25]	8715	1			T4	1		T6	21		T7	18
valid_sources[0x26]	10712	1			T4	9		T6	21		T7	26
valid_sources[0x27]	7066	1			T6	4		T7	22		T10	26
valid_sources[0x28]	11130	1			T1	1		T6	40		T7	21
valid_sources[0x29]	10784	1			T4	8		T6	10		T7	27
valid_sources[0x2a]	10989	1			T4	3		T6	5		T7	23
valid_sources[0x2b]	6614	1			T6	22		T7	19		T9	4
valid_sources[0x2c]	6773	1			T4	1		T6	9		T7	25
valid_sources[0x2d]	7202	1			T3	4		T4	7		T6	8
valid_sources[0x2e]	11539	1			T4	6		T6	14		T7	20
valid_sources[0x2f]	6926	1			T4	6		T6	22		T7	16
valid_sources[0x30]	14347	1			T2	37		T3	1		T4	5
valid_sources[0x31]	14899	1			T4	3		T6	7		T7	26
valid_sources[0x32]	11500	1			T3	2		T4	2		T6	7
valid_sources[0x33]	7298	1			T1	1		T4	5		T6	28
valid_sources[0x34]	9606	1			T4	7		T6	25		T7	26
valid_sources[0x35]	9647	1			T4	10		T6	16		T7	18
valid_sources[0x36]	8169	1			T6	24		T7	17		T9	7
valid_sources[0x37]	8495	1			T6	11		T7	22		T9	1
valid_sources[0x38]	7375	1			T6	11		T7	29		T9	6
valid_sources[0x39]	7270	1			T6	3		T7	24		T9	1
valid_sources[0x3a]	10213	1			T6	27		T7	22		T9	5
valid_sources[0x3b]	7142	1			T6	22		T7	18		T9	1
valid_sources[0x3c]	10929	1			T4	3		T6	16		T7	19
valid_sources[0x3d]	7405	1			T4	1		T6	4		T7	29
valid_sources[0x3e]	6971	1			T6	6		T7	22		T9	4
valid_sources[0x3f]	6886	1			T6	10		T7	20		T9	3
valid_sources[0x40]	11590	1			T4	5		T6	20		T7	29
valid_sources[0x41]	7904	1			T4	7		T6	11		T7	19
valid_sources[0x42]	6958	1			T6	3		T7	20		T9	8
valid_sources[0x43]	9823	1			T6	6		T7	18		T9	2
valid_sources[0x44]	6915	1			T4	1		T6	15		T7	22
valid_sources[0x45]	6919	1			T4	1		T6	8		T7	22
valid_sources[0x46]	12066	1			T4	1		T6	8		T7	25
valid_sources[0x47]	7320	1			T4	4		T6	9		T7	26
valid_sources[0x48]	10243	1			T6	19		T7	17		T9	1
valid_sources[0x49]	7719	1			T4	10		T7	54		T9	1
valid_sources[0x4a]	15721	1			T4	1		T6	1		T7	17
valid_sources[0x4b]	7153	1			T4	3		T6	8		T7	19
valid_sources[0x4c]	7944	1			T4	1		T7	16		T9	1
valid_sources[0x4d]	8302	1			T1	2		T4	1		T7	23
valid_sources[0x4e]	9759	1			T3	1		T6	13		T7	22
valid_sources[0x4f]	11424	1			T1	1		T4	3		T6	4
valid_sources[0x50]	7147	1			T4	2		T6	2		T7	17
valid_sources[0x51]	8056	1			T4	2		T6	9		T7	27
valid_sources[0x52]	8661	1			T4	3		T6	24		T7	29
valid_sources[0x53]	8908	1			T3	2		T4	4		T7	16
valid_sources[0x54]	7096	1			T3	4		T6	24		T7	24
valid_sources[0x55]	6483	1			T6	9		T7	18		T9	2
valid_sources[0x56]	6975	1			T4	3		T6	45		T7	18
valid_sources[0x57]	11128	1			T3	6		T6	8		T7	18
valid_sources[0x58]	8919	1			T2	89		T6	29		T7	23
valid_sources[0x59]	7436	1			T6	10		T7	15		T8	18
valid_sources[0x5a]	11378	1			T4	15		T6	1		T7	12
valid_sources[0x5b]	7028	1			T4	6		T6	13		T7	25
valid_sources[0x5c]	8616	1			T5	15		T6	6		T7	25
valid_sources[0x5d]	8136	1			T4	12		T6	10		T7	18
valid_sources[0x5e]	11277	1			T4	6		T6	9		T7	16
valid_sources[0x5f]	11245	1			T1	1		T4	7		T6	4
valid_sources[0x60]	10763	1			T4	3		T6	7		T7	17
valid_sources[0x61]	7126	1			T4	5		T7	22		T9	1
valid_sources[0x62]	7221	1			T6	7		T7	22		T9	7
valid_sources[0x63]	12696	1			T4	1		T6	16		T7	143
valid_sources[0x64]	7473	1			T7	196		T9	6		T10	37
valid_sources[0x65]	6845	1			T4	4		T6	4		T7	22
valid_sources[0x66]	7650	1			T6	3		T7	23		T9	5
valid_sources[0x67]	10613	1			T1	2		T4	11		T7	26
valid_sources[0x68]	7032	1			T4	26		T6	23		T7	16
valid_sources[0x69]	7761	1			T4	2		T6	1		T7	57
valid_sources[0x6a]	7289	1			T3	1		T4	3		T7	20
valid_sources[0x6b]	6903	1			T6	7		T7	17		T9	2
valid_sources[0x6c]	8211	1			T4	4		T6	9		T7	28
valid_sources[0x6d]	7053	1			T4	10		T6	18		T7	27
valid_sources[0x6e]	9850	1			T6	9		T7	216		T8	22
valid_sources[0x6f]	27590	1			T6	11		T7	20		T10	22
valid_sources[0x70]	12352	1			T6	12		T7	21		T8	26
valid_sources[0x71]	7715	1			T4	1		T7	25		T9	2
valid_sources[0x72]	8881	1			T6	13		T7	17		T9	2
valid_sources[0x73]	6724	1			T4	1		T6	11		T7	18
valid_sources[0x74]	6769	1			T4	3		T6	20		T7	55
valid_sources[0x75]	7077	1			T4	4		T6	11		T7	22
valid_sources[0x76]	7405	1			T4	1		T6	46		T7	28
valid_sources[0x77]	17279	1			T3	1		T4	8		T6	10
valid_sources[0x78]	11561	1			T3	1		T4	2		T6	1
valid_sources[0x79]	8178	1			T4	4		T5	3		T6	11
valid_sources[0x7a]	11134	1			T4	5		T6	15		T7	23
valid_sources[0x7b]	15686	1			T1	1		T4	6		T6	5
valid_sources[0x7c]	7518	1			T4	3		T5	15		T6	27
valid_sources[0x7d]	7015	1			T5	18		T6	7		T7	22
valid_sources[0x7e]	11689	1			T4	6		T6	10		T7	140
valid_sources[0x7f]	14837	1			T4	5		T6	3		T7	24
valid_sources[0x80]	6995	1			T4	6		T6	4		T7	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1014406

1

T2

39

T4

418

T5

301

values[0x0]

all_enables

biggest_size

81366

1

T1

8

T2

18

T3

18

values[0x1]

all_enables

biggest_size

59370

1

T1

6

T2

4

T3

9