Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	32761	1			T4	6		T6	21		T7	21
auto[PWRUP]	116	1			T16	1		T49	2		T53	2
auto[ONEST_0]	72	1			T37	1		T223	2		T165	1
auto[ONEST_021]	17	1			T224	1		T25	1		T225	1
auto[ONEST_1]	75	1			T16	1		T41	2		T51	1
auto[ONEST_DONE]	7	1			T226	1		T227	1		T228	1
auto[LP_0]	143	1			T14	1		T16	4		T49	2
auto[LP_021]	26	1			T14	1		T49	1		T51	1
auto[LP_1]	152	1			T14	1		T16	1		T53	4
auto[LP_EVAL]	65	1			T14	1		T49	1		T41	3
auto[LP_SLP]	519	1			T14	5		T16	6		T49	2
auto[LP_PWRUP]	21	1			T49	2		T165	1		T229	2
auto[NP_0]	137	1			T14	2		T16	2		T40	1
auto[NP_021]	33	1			T16	2		T44	2		T165	1
auto[NP_1]	193	1			T14	2		T16	2		T49	1
auto[NP_EVAL]	34	1			T16	2		T40	1		T51	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T230

1

T231

1

T232

1

min

32179

1

T4

6

T6

21

T7

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	32185	1			T4	6		T6	21		T7	21
pow[0x1]	10	1			T233	1		T234	1		T235	1
pow[0x2]	13	1			T14	1		T236	1		T237	1
pow[0x3]	28	1			T238	1		T60	1		T239	1
pow[0x4]	75	1			T16	2		T49	1		T43	1
pow[0x5]	155	1			T14	2		T16	1		T41	1
pow[0x6]	280	1			T14	2		T16	3		T49	1
pow[0x7]	535	1			T14	5		T16	7		T40	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

181

1

T14

1

T16

7

T49

1

min

31682

1

T4

6

T6

21

T7

21

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31683	1			T4	6		T6	21		T7	21
pow[0x6]	2	1			T240	1		T241	1		-	-
pow[0x7]	3	1			T242	1		T243	1		T244	1
pow[0x8]	10	1			T19	1		T245	1		T246	1
pow[0x9]	10	1			T44	1		T224	1		T247	1
pow[0xa]	20	1			T51	1		T44	1		T236	1
pow[0xb]	45	1			T14	1		T51	1		T237	1
pow[0xc]	86	1			T51	3		T44	1		T236	1
pow[0xd]	163	1			T14	1		T16	2		T41	1
pow[0xe]	293	1			T14	4		T16	4		T49	6
pow[0xf]	605	1			T14	6		T16	3		T49	7