Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2380	1			T5	5		T14	23		T50	3
auto[PWRUP]	139	1			T17	1		T53	1		T51	5
auto[ONEST_0]	83	1			T17	2		T41	1		T53	1
auto[ONEST_021]	21	1			T40	1		T49	2		T53	2
auto[ONEST_1]	88	1			T5	1		T40	1		T49	1
auto[ONEST_DONE]	4	1			T14	1		T375	1		T376	1
auto[LP_0]	157	1			T14	1		T16	3		T40	1
auto[LP_021]	33	1			T5	1		T43	1		T37	1
auto[LP_1]	158	1			T14	2		T16	1		T49	1
auto[LP_EVAL]	64	1			T40	2		T41	3		T53	1
auto[LP_SLP]	545	1			T5	1		T14	11		T16	5
auto[LP_PWRUP]	33	1			T51	1		T44	1		T229	2
auto[NP_0]	214	1			T14	2		T16	2		T40	3
auto[NP_021]	65	1			T16	1		T41	2		T43	1
auto[NP_1]	227	1			T5	2		T14	1		T17	1
auto[NP_EVAL]	33	1			T14	1		T16	1		T43	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T377

1

T223

1

T165

1

min

2015

1

T5

10

T14

12

T50

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2027	1			T5	10		T14	12		T50	3
pow[0x1]	17	1			T40	1		T17	1		T165	1
pow[0x2]	23	1			T53	1		T223	2		T225	1
pow[0x3]	31	1			T49	1		T42	1		T39	2
pow[0x4]	79	1			T16	1		T49	3		T41	1
pow[0x5]	145	1			T14	2		T16	1		T49	2
pow[0x6]	311	1			T14	5		T16	4		T40	1
pow[0x7]	548	1			T14	11		T16	6		T40	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

213

1

T14

4

T16

1

T40

1

min

1391

1

T5

10

T14

2

T50

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1398	1			T5	10		T14	2		T50	3
pow[0x1]	16	1			T40	1		T18	1		T21	1
pow[0x2]	17	1			T378	1		T271	1		T246	2
pow[0x3]	38	1			T40	1		T42	1		T43	1
pow[0x4]	64	1			T17	1		T41	4		T43	4
pow[0x5]	1	1			T379	1		-	-		-	-
pow[0x6]	1	1			T224	1		-	-		-	-
pow[0x7]	3	1			T49	1		T231	1		T244	1
pow[0x8]	3	1			T44	1		T380	1		T228	1
pow[0x9]	11	1			T237	1		T375	1		T381	1
pow[0xa]	14	1			T53	1		T51	1		T224	1
pow[0xb]	41	1			T14	1		T53	1		T43	1
pow[0xc]	84	1			T14	1		T49	2		T41	1
pow[0xd]	164	1			T14	3		T16	2		T53	3
pow[0xe]	311	1			T14	2		T16	1		T40	1
pow[0xf]	613	1			T14	9		T16	4		T49	2