Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1170406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1140328

1

T1

959

T2

970

T3

1384

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2021443	1			T1	1713		T2	1713		T3	2454
values[0x0]	144143	1			T1	96		T2	102		T3	140
values[0x1]	145148	1			T1	110		T2	97		T3	152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	937789	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1372945

1

T1

1150

T2

1143

T3

1636

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6719	1			T1	30		T2	5		T3	24
valid_sources[0x01]	9444	1			T1	17		T2	8		T3	13
valid_sources[0x02]	12016	1			T2	12		T3	13		T4	10
valid_sources[0x03]	14062	1			T1	11		T2	15		T3	17
valid_sources[0x04]	6509	1			T2	11		T3	10		T4	12
valid_sources[0x05]	6762	1			T1	28		T2	7		T3	4
valid_sources[0x06]	6834	1			T1	6		T2	4		T3	5
valid_sources[0x07]	11581	1			T2	6		T3	5		T4	13
valid_sources[0x08]	7387	1			T1	2		T2	9		T3	10
valid_sources[0x09]	12511	1			T1	1		T2	14		T3	1
valid_sources[0x0a]	7196	1			T2	6		T3	7		T4	19
valid_sources[0x0b]	9268	1			T1	8		T2	8		T3	3
valid_sources[0x0c]	7162	1			T2	12		T3	11		T4	10
valid_sources[0x0d]	9844	1			T1	9		T2	4		T3	8
valid_sources[0x0e]	6861	1			T1	3		T2	12		T3	4
valid_sources[0x0f]	11167	1			T2	5		T3	4		T4	8
valid_sources[0x10]	11067	1			T1	6		T2	5		T3	6
valid_sources[0x11]	14302	1			T1	10		T2	10		T3	14
valid_sources[0x12]	9351	1			T2	1		T3	4		T4	7
valid_sources[0x13]	6658	1			T1	2		T2	5		T3	3
valid_sources[0x14]	6513	1			T1	20		T2	4		T3	5
valid_sources[0x15]	7890	1			T2	4		T3	2		T4	7
valid_sources[0x16]	6974	1			T1	2		T2	3		T3	7
valid_sources[0x17]	6818	1			T1	5		T2	13		T3	1
valid_sources[0x18]	6565	1			T1	9		T2	10		T3	1
valid_sources[0x19]	6773	1			T2	1		T3	18		T4	7
valid_sources[0x1a]	10657	1			T1	9		T2	7		T3	3
valid_sources[0x1b]	7165	1			T1	2		T2	5		T3	7
valid_sources[0x1c]	11421	1			T2	10		T3	9		T4	16
valid_sources[0x1d]	11304	1			T2	9		T3	4		T4	17
valid_sources[0x1e]	7988	1			T2	8		T3	5		T4	14
valid_sources[0x1f]	7682	1			T1	5		T2	5		T3	23
valid_sources[0x20]	18194	1			T1	5		T2	1		T3	5
valid_sources[0x21]	7573	1			T2	5		T3	8		T4	10
valid_sources[0x22]	7546	1			T2	2		T3	12		T4	14
valid_sources[0x23]	7954	1			T1	1		T2	2		T3	13
valid_sources[0x24]	8611	1			T1	3		T2	5		T3	3
valid_sources[0x25]	9975	1			T1	3		T2	1		T3	6
valid_sources[0x26]	12366	1			T2	5		T3	2		T4	9
valid_sources[0x27]	7024	1			T1	8		T2	9		T3	13
valid_sources[0x28]	12090	1			T1	22		T2	4		T3	6
valid_sources[0x29]	7010	1			T1	4		T2	19		T3	6
valid_sources[0x2a]	21011	1			T2	8		T3	2		T4	7
valid_sources[0x2b]	6426	1			T2	3		T3	4		T4	9
valid_sources[0x2c]	11605	1			T1	11		T2	17		T3	6
valid_sources[0x2d]	12726	1			T1	6		T2	3		T3	4
valid_sources[0x2e]	6775	1			T1	4		T2	11		T3	7
valid_sources[0x2f]	17935	1			T1	2		T2	3		T3	6
valid_sources[0x30]	6853	1			T1	37		T2	4		T3	1
valid_sources[0x31]	6780	1			T1	4		T2	5		T4	8
valid_sources[0x32]	6526	1			T1	14		T2	8		T3	9
valid_sources[0x33]	7226	1			T1	38		T2	5		T3	8
valid_sources[0x34]	7129	1			T3	6		T4	10		T5	42
valid_sources[0x35]	7346	1			T2	4		T3	5		T4	11
valid_sources[0x36]	7958	1			T1	9		T2	7		T3	5
valid_sources[0x37]	6835	1			T1	2		T2	9		T4	8
valid_sources[0x38]	7772	1			T1	4		T2	7		T3	2
valid_sources[0x39]	6605	1			T1	16		T2	9		T3	13
valid_sources[0x3a]	10044	1			T1	6		T2	14		T3	12
valid_sources[0x3b]	7832	1			T1	12		T2	9		T3	1
valid_sources[0x3c]	6801	1			T2	6		T3	15		T4	10
valid_sources[0x3d]	9589	1			T1	4		T2	2		T3	3
valid_sources[0x3e]	11214	1			T1	5		T2	20		T3	9
valid_sources[0x3f]	11285	1			T1	1		T2	7		T3	7
valid_sources[0x40]	14117	1			T1	19		T2	8		T3	12
valid_sources[0x41]	7738	1			T2	20		T3	17		T4	9
valid_sources[0x42]	7589	1			T1	3		T2	6		T3	4
valid_sources[0x43]	7743	1			T2	9		T3	4		T4	7
valid_sources[0x44]	11517	1			T2	1		T3	4		T4	10
valid_sources[0x45]	6544	1			T1	11		T2	9		T3	9
valid_sources[0x46]	6741	1			T1	4		T2	5		T3	12
valid_sources[0x47]	6733	1			T1	5		T4	14		T5	21
valid_sources[0x48]	8202	1			T2	6		T3	15		T4	7
valid_sources[0x49]	12241	1			T1	21		T2	8		T3	3
valid_sources[0x4a]	7404	1			T2	1		T3	8		T4	6
valid_sources[0x4b]	6985	1			T1	4		T2	5		T3	6
valid_sources[0x4c]	10044	1			T1	42		T2	5		T3	8
valid_sources[0x4d]	7356	1			T1	10		T2	10		T3	6
valid_sources[0x4e]	7196	1			T2	5		T3	13		T4	11
valid_sources[0x4f]	7750	1			T1	13		T2	11		T3	15
valid_sources[0x50]	7492	1			T1	40		T2	8		T3	13
valid_sources[0x51]	18688	1			T1	14		T2	7		T3	19
valid_sources[0x52]	9047	1			T1	3		T2	3		T3	7
valid_sources[0x53]	6643	1			T1	1		T2	8		T3	1
valid_sources[0x54]	6911	1			T1	4		T2	7		T3	3
valid_sources[0x55]	7097	1			T1	5		T2	15		T3	14
valid_sources[0x56]	11565	1			T2	4		T3	8		T4	13
valid_sources[0x57]	7376	1			T1	22		T2	2		T3	5
valid_sources[0x58]	11603	1			T2	7		T3	5		T4	11
valid_sources[0x59]	6415	1			T1	12		T2	7		T3	18
valid_sources[0x5a]	7575	1			T1	4		T2	14		T3	8
valid_sources[0x5b]	11275	1			T1	4		T2	18		T3	6
valid_sources[0x5c]	11219	1			T1	8		T2	2		T3	4
valid_sources[0x5d]	6997	1			T1	11		T2	6		T3	11
valid_sources[0x5e]	7058	1			T1	3		T2	8		T3	9
valid_sources[0x5f]	6671	1			T1	3		T2	2		T3	8
valid_sources[0x60]	7989	1			T2	8		T3	9		T4	14
valid_sources[0x61]	6709	1			T1	3		T2	12		T3	15
valid_sources[0x62]	7757	1			T1	7		T2	7		T3	5
valid_sources[0x63]	14949	1			T1	15		T2	2		T3	7
valid_sources[0x64]	7573	1			T1	2		T2	3		T3	8
valid_sources[0x65]	7020	1			T1	12		T2	4		T3	9
valid_sources[0x66]	9088	1			T1	29		T2	9		T3	15
valid_sources[0x67]	6781	1			T2	7		T3	5		T4	9
valid_sources[0x68]	8398	1			T1	13		T2	2		T3	17
valid_sources[0x69]	7253	1			T1	4		T2	8		T3	8
valid_sources[0x6a]	7868	1			T1	1		T2	15		T3	6
valid_sources[0x6b]	6896	1			T2	2		T3	5		T4	12
valid_sources[0x6c]	7689	1			T1	8		T2	7		T3	1
valid_sources[0x6d]	6943	1			T1	3		T2	11		T3	5
valid_sources[0x6e]	7558	1			T1	13		T2	7		T3	8
valid_sources[0x6f]	7571	1			T1	12		T2	9		T3	7
valid_sources[0x70]	7195	1			T1	2		T2	3		T3	6
valid_sources[0x71]	14235	1			T1	1		T2	13		T3	3
valid_sources[0x72]	7158	1			T1	10		T2	7		T3	8
valid_sources[0x73]	11408	1			T2	5		T3	3		T4	11
valid_sources[0x74]	7905	1			T2	4		T3	6		T4	11
valid_sources[0x75]	8185	1			T1	2		T2	2		T3	10
valid_sources[0x76]	7106	1			T1	13		T2	8		T3	5
valid_sources[0x77]	10638	1			T1	3		T2	5		T3	3
valid_sources[0x78]	7739	1			T1	11		T2	15		T3	12
valid_sources[0x79]	7538	1			T1	1		T2	2		T3	9
valid_sources[0x7a]	6223	1			T1	5		T2	3		T3	5
valid_sources[0x7b]	7422	1			T1	22		T2	7		T3	10
valid_sources[0x7c]	18100	1			T1	5		T2	4		T3	4
valid_sources[0x7d]	6682	1			T1	16		T2	6		T3	4
valid_sources[0x7e]	17253	1			T1	22		T2	4		T3	21
valid_sources[0x7f]	6895	1			T1	17		T2	13		T3	13
valid_sources[0x80]	7131	1			T1	1		T2	9		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1006806

1

T1

865

T2

876

T3

1241

values[0x0]

all_enables

biggest_size

77934

1

T1

50

T2

54

T3

77

values[0x1]

all_enables

biggest_size

55588

1

T1

44

T2

40

T3

66