Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29479	1			T1	13		T2	13		T3	28
auto[PWRUP]	108	1			T25	3		T41	1		T43	2
auto[ONEST_0]	76	1			T11	2		T25	1		T42	1
auto[ONEST_021]	20	1			T45	1		T172	1		T225	1
auto[ONEST_1]	85	1			T11	1		T25	2		T41	1
auto[ONEST_DONE]	5	1			T43	1		T95	1		T226	1
auto[LP_0]	131	1			T25	5		T42	2		T41	1
auto[LP_021]	39	1			T14	1		T42	1		T41	1
auto[LP_1]	121	1			T25	3		T42	1		T41	2
auto[LP_EVAL]	61	1			T11	2		T14	3		T25	1
auto[LP_SLP]	554	1			T11	8		T14	1		T25	13
auto[LP_PWRUP]	21	1			T25	1		T42	2		T43	1
auto[NP_0]	190	1			T11	4		T25	4		T41	4
auto[NP_021]	48	1			T227	1		T95	1		T172	1
auto[NP_1]	161	1			T11	4		T25	4		T42	1
auto[NP_EVAL]	31	1			T11	1		T41	1		T17	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T228

1

T229

1

T230

1

min

28955

1

T1

13

T2

13

T3

28

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28963	1			T1	13		T2	13		T3	28
pow[0x1]	15	1			T41	1		T231	1		T172	1
pow[0x2]	9	1			T14	1		T44	1		T45	1
pow[0x3]	37	1			T25	4		T232	1		T233	3
pow[0x4]	68	1			T41	1		T43	1		T234	1
pow[0x5]	143	1			T11	2		T25	4		T41	2
pow[0x6]	265	1			T11	3		T14	2		T25	5
pow[0x7]	583	1			T11	3		T25	13		T42	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

201

1

T11

5

T14

1

T25

8

min

28457

1

T1

13

T2

13

T3

28

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1
pow[0x8]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28457	1			T1	13		T2	13		T3	28
pow[0x4]	2	1			T95	1		T235	1		-	-
pow[0x5]	1	1			T101	1		-	-		-	-
pow[0x7]	2	1			T229	1		T230	1		-	-
pow[0x9]	8	1			T172	1		T236	1		T237	1
pow[0xa]	18	1			T14	1		T238	1		T229	1
pow[0xb]	35	1			T25	1		T232	1		T233	2
pow[0xc]	78	1			T11	2		T25	4		T42	1
pow[0xd]	182	1			T11	4		T25	2		T42	3
pow[0xe]	322	1			T11	5		T14	2		T25	8
pow[0xf]	608	1			T11	6		T14	3		T25	14