Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2361	1			T11	13		T13	5		T14	12
auto[PWRUP]	121	1			T11	2		T25	3		T42	2
auto[ONEST_0]	82	1			T25	2		T41	1		T233	1
auto[ONEST_021]	14	1			T42	1		T44	1		T172	1
auto[ONEST_1]	97	1			T11	1		T25	2		T42	3
auto[ONEST_DONE]	4	1			T231	1		T371	1		T372	1
auto[LP_0]	153	1			T11	2		T25	4		T42	2
auto[LP_021]	32	1			T232	1		T17	1		T19	1
auto[LP_1]	148	1			T11	2		T25	3		T41	2
auto[LP_EVAL]	65	1			T11	1		T41	1		T233	2
auto[LP_SLP]	580	1			T11	7		T14	3		T25	10
auto[LP_PWRUP]	42	1			T25	1		T234	2		T231	1
auto[NP_0]	207	1			T11	3		T14	3		T25	1
auto[NP_021]	60	1			T14	1		T41	2		T16	1
auto[NP_1]	240	1			T11	1		T25	4		T42	2
auto[NP_EVAL]	34	1			T37	1		T373	1		T40	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T25

2

T238

1

T371

1

min

2078

1

T11

10

T13

5

T14

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2090	1			T11	10		T13	5		T14	11
pow[0x1]	10	1			T25	1		T231	1		T201	1
pow[0x2]	16	1			T11	1		T25	1		T43	1
pow[0x3]	35	1			T25	1		T41	1		T232	1
pow[0x4]	56	1			T41	1		T232	1		T233	1
pow[0x5]	132	1			T25	4		T42	2		T41	3
pow[0x6]	267	1			T11	1		T25	6		T42	1
pow[0x7]	549	1			T11	8		T14	2		T25	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

197

1

T25

2

T42

2

T41

2

min

1377

1

T11

3

T13

5

T14

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1385	1			T11	3		T13	5		T14	8
pow[0x1]	9	1			T18	1		T304	1		T339	1
pow[0x2]	23	1			T16	2		T37	1		T38	1
pow[0x3]	64	1			T14	1		T15	1		T16	1
pow[0x4]	64	1			T15	3		T17	1		T38	1
pow[0x5]	3	1			T225	1		T201	1		T374	1
pow[0x6]	3	1			T231	1		T375	1		T376	1
pow[0x7]	1	1			T313	1		-	-		-	-
pow[0x8]	2	1			T11	1		T373	1		-	-
pow[0x9]	14	1			T11	1		T227	1		T23	1
pow[0xa]	21	1			T41	1		T233	1		T44	1
pow[0xb]	30	1			T11	1		T14	2		T25	1
pow[0xc]	80	1			T25	2		T41	2		T43	1
pow[0xd]	142	1			T11	2		T14	1		T25	2
pow[0xe]	307	1			T11	3		T25	6		T42	3
pow[0xf]	645	1			T11	9		T14	2		T25	11