Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1219104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1194981

1

T1

436

T2

56

T3

1408

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2118159	1			T2	81		T3	2468		T5	257
values[0x0]	148098	1			T1	548		T2	39		T3	160
values[0x1]	147828	1			T1	519		T2	24		T3	147

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	975987	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1438098

1

T1

517

T2

71

T3

1690

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12857	1			T2	1		T3	11		T5	2
valid_sources[0x01]	7479	1			T2	1		T3	12		T5	2
valid_sources[0x02]	8605	1			T2	2		T3	13		T6	58
valid_sources[0x03]	11842	1			T3	4		T5	1		T6	89
valid_sources[0x04]	7425	1			T3	10		T6	19		T7	8
valid_sources[0x05]	16176	1			T3	6		T4	1		T6	50
valid_sources[0x06]	7512	1			T3	14		T5	5		T6	18
valid_sources[0x07]	8660	1			T3	4		T5	4		T6	32
valid_sources[0x08]	10008	1			T2	1		T3	10		T6	17
valid_sources[0x09]	8083	1			T3	3		T5	17		T6	30
valid_sources[0x0a]	11556	1			T3	22		T6	14		T7	48
valid_sources[0x0b]	15226	1			T3	5		T6	23		T7	1
valid_sources[0x0c]	7210	1			T3	9		T6	55		T7	4
valid_sources[0x0d]	12915	1			T3	8		T4	5		T5	1
valid_sources[0x0e]	8422	1			T3	9		T5	1		T6	24
valid_sources[0x0f]	8470	1			T3	15		T6	17		T7	6
valid_sources[0x10]	8158	1			T3	11		T5	1		T6	25
valid_sources[0x11]	7449	1			T3	2		T5	3		T6	14
valid_sources[0x12]	10987	1			T3	8		T5	2		T6	16
valid_sources[0x13]	10007	1			T3	6		T6	37		T7	20
valid_sources[0x14]	7623	1			T2	1		T3	25		T6	7
valid_sources[0x15]	7804	1			T2	1		T3	3		T5	1
valid_sources[0x16]	7282	1			T3	16		T6	24		T7	15
valid_sources[0x17]	7441	1			T3	14		T5	1		T6	39
valid_sources[0x18]	10534	1			T2	2		T3	11		T6	38
valid_sources[0x19]	9312	1			T2	1		T3	13		T6	27
valid_sources[0x1a]	10139	1			T3	7		T5	16		T6	29
valid_sources[0x1b]	8151	1			T2	1		T3	26		T6	26
valid_sources[0x1c]	7686	1			T3	10		T4	6		T6	33
valid_sources[0x1d]	9062	1			T3	16		T5	4		T6	11
valid_sources[0x1e]	7723	1			T2	3		T3	5		T6	21
valid_sources[0x1f]	11679	1			T3	1		T5	34		T6	21
valid_sources[0x20]	7097	1			T2	1		T3	10		T5	2
valid_sources[0x21]	7325	1			T2	2		T3	9		T5	1
valid_sources[0x22]	8412	1			T3	12		T5	8		T6	11
valid_sources[0x23]	7029	1			T2	2		T3	7		T5	2
valid_sources[0x24]	7126	1			T3	4		T4	1		T6	59
valid_sources[0x25]	7404	1			T2	1		T3	13		T5	2
valid_sources[0x26]	9860	1			T3	8		T4	1		T6	25
valid_sources[0x27]	7396	1			T3	11		T6	45		T7	11
valid_sources[0x28]	11864	1			T3	5		T6	28		T15	1
valid_sources[0x29]	8911	1			T3	7		T6	29		T7	21
valid_sources[0x2a]	11424	1			T3	14		T6	19		T7	45
valid_sources[0x2b]	9409	1			T3	14		T6	29		T8	2
valid_sources[0x2c]	12094	1			T3	23		T5	1		T6	16
valid_sources[0x2d]	7470	1			T2	1		T3	11		T5	3
valid_sources[0x2e]	10652	1			T3	8		T6	19		T7	28
valid_sources[0x2f]	7829	1			T3	24		T6	16		T9	29
valid_sources[0x30]	7475	1			T2	2		T3	12		T5	2
valid_sources[0x31]	17859	1			T3	14		T6	96		T7	19
valid_sources[0x32]	13038	1			T3	13		T6	43		T7	27
valid_sources[0x33]	12137	1			T2	1		T3	9		T6	47
valid_sources[0x34]	21518	1			T3	10		T6	26		T7	18
valid_sources[0x35]	7470	1			T3	12		T6	56		T7	29
valid_sources[0x36]	13011	1			T3	12		T5	2		T6	29
valid_sources[0x37]	8519	1			T2	2		T3	33		T6	31
valid_sources[0x38]	8670	1			T3	5		T5	13		T6	10
valid_sources[0x39]	7252	1			T3	20		T5	2		T6	33
valid_sources[0x3a]	9130	1			T2	1		T3	6		T5	3
valid_sources[0x3b]	15182	1			T3	11		T5	2		T6	13
valid_sources[0x3c]	8178	1			T3	14		T5	15		T6	34
valid_sources[0x3d]	7305	1			T3	16		T6	15		T7	12
valid_sources[0x3e]	7107	1			T2	3		T3	14		T6	37
valid_sources[0x3f]	7374	1			T3	13		T6	27		T7	14
valid_sources[0x40]	7271	1			T2	3		T3	6		T6	39
valid_sources[0x41]	9412	1			T2	4		T3	1		T4	3
valid_sources[0x42]	7477	1			T3	30		T5	2		T6	77
valid_sources[0x43]	11832	1			T2	1		T3	12		T5	10
valid_sources[0x44]	10436	1			T3	11		T6	29		T7	29
valid_sources[0x45]	20513	1			T2	1		T3	5		T6	55
valid_sources[0x46]	9338	1			T3	11		T6	40		T7	26
valid_sources[0x47]	7366	1			T3	5		T6	25		T7	4
valid_sources[0x48]	7637	1			T3	11		T5	1		T6	16
valid_sources[0x49]	8043	1			T3	20		T5	1		T6	22
valid_sources[0x4a]	7770	1			T2	1		T3	14		T6	31
valid_sources[0x4b]	7447	1			T3	13		T6	24		T7	16
valid_sources[0x4c]	10233	1			T3	5		T5	1		T6	32
valid_sources[0x4d]	8456	1			T3	8		T6	29		T7	8
valid_sources[0x4e]	7325	1			T3	15		T6	70		T7	1
valid_sources[0x4f]	10705	1			T3	9		T6	29		T7	8
valid_sources[0x50]	15945	1			T3	7		T5	7		T6	48
valid_sources[0x51]	8548	1			T2	2		T3	11		T6	18
valid_sources[0x52]	7622	1			T2	1		T3	20		T6	20
valid_sources[0x53]	7117	1			T3	10		T6	35		T15	1
valid_sources[0x54]	7382	1			T2	3		T3	5		T6	53
valid_sources[0x55]	11842	1			T3	2		T5	3		T6	43
valid_sources[0x56]	8266	1			T2	1		T3	13		T5	1
valid_sources[0x57]	7711	1			T3	22		T5	3		T6	29
valid_sources[0x58]	9308	1			T2	1		T3	8		T6	15
valid_sources[0x59]	7360	1			T2	1		T3	9		T6	44
valid_sources[0x5a]	8936	1			T3	1		T5	3		T6	38
valid_sources[0x5b]	9809	1			T3	10		T6	32		T7	5
valid_sources[0x5c]	7686	1			T2	1		T3	12		T5	59
valid_sources[0x5d]	7586	1			T3	11		T6	29		T7	22
valid_sources[0x5e]	8519	1			T2	1		T3	8		T6	53
valid_sources[0x5f]	7402	1			T3	12		T6	17		T7	7
valid_sources[0x60]	7097	1			T3	22		T6	42		T7	11
valid_sources[0x61]	10086	1			T2	3		T3	6		T6	27
valid_sources[0x62]	7676	1			T3	12		T6	14		T7	14
valid_sources[0x63]	7613	1			T3	16		T5	13		T6	24
valid_sources[0x64]	7413	1			T2	1		T3	10		T6	52
valid_sources[0x65]	15065	1			T3	27		T6	25		T7	35
valid_sources[0x66]	24344	1			T3	13		T6	41		T7	12
valid_sources[0x67]	7520	1			T3	13		T5	3		T6	24
valid_sources[0x68]	24658	1			T3	10		T5	1		T6	38
valid_sources[0x69]	7343	1			T2	1		T3	11		T6	37
valid_sources[0x6a]	8234	1			T3	4		T5	5		T6	20
valid_sources[0x6b]	7272	1			T3	5		T5	4		T6	47
valid_sources[0x6c]	11736	1			T2	1		T3	5		T4	1
valid_sources[0x6d]	8565	1			T3	16		T5	9		T6	58
valid_sources[0x6e]	14011	1			T3	5		T6	32		T7	23
valid_sources[0x6f]	10768	1			T2	1		T3	5		T5	3
valid_sources[0x70]	7726	1			T3	13		T5	10		T6	52
valid_sources[0x71]	7100	1			T3	5		T5	1		T6	67
valid_sources[0x72]	7624	1			T3	12		T5	1		T6	130
valid_sources[0x73]	7363	1			T3	19		T5	2		T6	33
valid_sources[0x74]	8157	1			T3	9		T5	1		T6	43
valid_sources[0x75]	7709	1			T3	6		T6	14		T7	9
valid_sources[0x76]	8296	1			T2	1		T3	10		T6	22
valid_sources[0x77]	9862	1			T3	12		T5	2		T6	13
valid_sources[0x78]	8198	1			T2	1		T3	11		T6	30
valid_sources[0x79]	7365	1			T3	9		T5	1		T6	54
valid_sources[0x7a]	7095	1			T2	1		T3	10		T6	54
valid_sources[0x7b]	11991	1			T2	1		T3	19		T5	1
valid_sources[0x7c]	10219	1			T3	17		T5	1		T6	41
valid_sources[0x7d]	8080	1			T3	14		T6	26		T7	15
valid_sources[0x7e]	11673	1			T2	1		T3	3		T5	1
valid_sources[0x7f]	7582	1			T3	14		T5	114		T6	53
valid_sources[0x80]	11695	1			T2	1		T3	11		T5	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1055696

1

T2

40

T3

1239

T5

108

values[0x0]

all_enables

biggest_size

81079

1

T1

262

T2

12

T3

99

values[0x1]

all_enables

biggest_size

58206

1

T1

174

T2

4

T3

70