Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31605	1			T1	256		T3	25		T5	29
auto[PWRUP]	105	1			T1	1		T5	1		T51	4
auto[ONEST_0]	83	1			T1	2		T51	2		T50	1
auto[ONEST_021]	13	1			T1	1		T51	1		T177	1
auto[ONEST_1]	92	1			T1	3		T14	1		T31	1
auto[ONEST_DONE]	3	1			T186	1		T187	1		T188	1
auto[LP_0]	104	1			T1	2		T5	1		T12	1
auto[LP_021]	21	1			T1	1		T31	1		T177	1
auto[LP_1]	132	1			T49	2		T51	1		T50	2
auto[LP_EVAL]	59	1			T1	1		T49	1		T51	1
auto[LP_SLP]	510	1			T1	8		T5	1		T12	1
auto[LP_PWRUP]	26	1			T51	1		T17	1		T177	2
auto[NP_0]	150	1			T1	1		T49	3		T51	2
auto[NP_021]	34	1			T189	1		T186	1		T190	1
auto[NP_1]	142	1			T1	3		T5	1		T49	5
auto[NP_EVAL]	27	1			T51	1		T52	1		T177	3

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T191

1

T192

1

T193

1

min

31075

1

T1

250

T3

25

T5

29

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31086	1			T1	250		T3	25		T5	29
pow[0x1]	9	1			T17	1		T52	2		T186	1
pow[0x2]	18	1			T31	1		T186	1		T39	2
pow[0x3]	29	1			T49	1		T31	1		T52	1
pow[0x4]	72	1			T1	1		T51	2		T50	1
pow[0x5]	117	1			T1	2		T51	1		T50	1
pow[0x6]	256	1			T1	5		T14	1		T49	5
pow[0x7]	510	1			T1	6		T5	1		T14	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

212

1

T1

2

T49

2

T51

4

min

30623

1

T1

241

T3

25

T5

28

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30623	1			T1	241		T3	25		T5	28
pow[0x3]	1	1			T192	1		-	-		-	-
pow[0x5]	2	1			T194	1		T195	1		-	-
pow[0x6]	1	1			T196	1		-	-		-	-
pow[0x7]	3	1			T197	1		T198	1		T87	1
pow[0x8]	6	1			T199	1		T200	1		T201	1
pow[0x9]	14	1			T31	1		T189	1		T202	1
pow[0xa]	12	1			T190	1		T199	1		T194	1
pow[0xb]	47	1			T1	1		T5	1		T14	1
pow[0xc]	70	1			T1	4		T12	1		T49	1
pow[0xd]	148	1			T1	2		T17	1		T31	1
pow[0xe]	284	1			T1	3		T5	1		T49	3
pow[0xf]	562	1			T1	7		T5	1		T14	1