Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2332	1			T1	20		T5	12		T12	17
auto[PWRUP]	105	1			T1	1		T51	2		T50	2
auto[ONEST_0]	67	1			T1	1		T51	1		T52	1
auto[ONEST_021]	16	1			T18	1		T40	1		T203	1
auto[ONEST_1]	108	1			T5	1		T49	2		T31	2
auto[ONEST_DONE]	4	1			T14	1		T204	1		T205	1
auto[LP_0]	132	1			T1	2		T5	3		T12	1
auto[LP_021]	26	1			T50	1		T189	1		T199	1
auto[LP_1]	144	1			T1	1		T49	2		T51	3
auto[LP_EVAL]	51	1			T1	1		T50	1		T17	1
auto[LP_SLP]	501	1			T1	4		T5	1		T12	3
auto[LP_PWRUP]	22	1			T50	1		T52	1		T190	1
auto[NP_0]	205	1			T1	2		T5	2		T12	6
auto[NP_021]	67	1			T14	1		T50	1		T31	2
auto[NP_1]	219	1			T1	1		T12	1		T14	4
auto[NP_EVAL]	32	1			T1	1		T49	1		T17	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T40

1

T192

1

T197

1

min

2013

1

T1

7

T5

13

T12

22

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2028	1			T1	7		T5	13		T12	22
pow[0x1]	7	1			T203	1		T206	1		T21	1
pow[0x2]	17	1			T51	1		T189	1		T200	1
pow[0x3]	38	1			T1	1		T49	2		T31	2
pow[0x4]	71	1			T49	2		T51	1		T50	2
pow[0x5]	129	1			T1	3		T51	2		T50	2
pow[0x6]	242	1			T1	5		T49	2		T51	2
pow[0x7]	500	1			T1	4		T5	1		T14	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

191

1

T1

3

T51

4

T50

1

min

1431

1

T1

3

T5

14

T12

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1443	1			T1	3		T5	14		T12	21
pow[0x1]	8	1			T39	1		T21	2		T207	1
pow[0x2]	33	1			T19	1		T84	3		T137	2
pow[0x3]	45	1			T12	1		T39	1		T40	1
pow[0x4]	63	1			T12	1		T14	5		T17	4
pow[0x8]	2	1			T192	1		T205	1		-	-
pow[0x9]	5	1			T202	1		T208	1		T209	1
pow[0xa]	19	1			T50	1		T31	1		T186	1
pow[0xb]	46	1			T1	1		T50	1		T31	1
pow[0xc]	62	1			T49	1		T31	1		T52	1
pow[0xd]	134	1			T1	1		T5	1		T49	2
pow[0xe]	290	1			T1	6		T12	1		T14	1
pow[0xf]	566	1			T1	6		T5	1		T12	3