Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1203544	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1175777

1

T1

2096

T2

6478

T3

1764

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2080857	1			T1	4025		T2	12339		T3	2638
values[0x0]	148626	1			T1	100		T2	389		T3	524
values[0x1]	149838	1			T1	127		T2	355		T3	553

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	964778	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1414543

1

T1

2551

T2

7771

T3

2144

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8901	1			T2	56		T3	14		T4	11
valid_sources[0x01]	7865	1			T1	12		T2	50		T3	7
valid_sources[0x02]	16640	1			T1	2		T2	50		T3	5
valid_sources[0x03]	8151	1			T1	4		T2	39		T3	9
valid_sources[0x04]	13981	1			T1	45		T2	50		T3	6
valid_sources[0x05]	6990	1			T1	27		T2	52		T3	14
valid_sources[0x06]	6671	1			T1	41		T2	48		T3	24
valid_sources[0x07]	11888	1			T1	74		T2	56		T3	19
valid_sources[0x08]	10135	1			T1	2		T2	44		T3	19
valid_sources[0x09]	11309	1			T1	3		T2	41		T3	7
valid_sources[0x0a]	9329	1			T2	44		T3	7		T4	3
valid_sources[0x0b]	6983	1			T1	16		T2	48		T3	91
valid_sources[0x0c]	13588	1			T1	10		T2	38		T3	10
valid_sources[0x0d]	9437	1			T1	3		T2	65		T3	5
valid_sources[0x0e]	10719	1			T1	57		T2	67		T3	13
valid_sources[0x0f]	6383	1			T1	5		T2	48		T3	11
valid_sources[0x10]	7642	1			T1	56		T2	55		T3	34
valid_sources[0x11]	7072	1			T2	47		T3	15		T4	9
valid_sources[0x12]	11255	1			T1	19		T2	39		T3	4
valid_sources[0x13]	7014	1			T1	30		T2	39		T3	40
valid_sources[0x14]	7010	1			T1	12		T2	68		T3	13
valid_sources[0x15]	8137	1			T1	53		T2	34		T3	14
valid_sources[0x16]	9594	1			T1	36		T2	83		T3	12
valid_sources[0x17]	23835	1			T1	11		T2	54		T3	6
valid_sources[0x18]	8463	1			T1	25		T2	36		T3	17
valid_sources[0x19]	6831	1			T1	9		T2	41		T3	28
valid_sources[0x1a]	11501	1			T1	7		T2	37		T3	26
valid_sources[0x1b]	6597	1			T1	8		T2	40		T3	25
valid_sources[0x1c]	7817	1			T2	71		T3	16		T4	8
valid_sources[0x1d]	20055	1			T1	11		T2	63		T3	9
valid_sources[0x1e]	6959	1			T2	48		T3	7		T4	13
valid_sources[0x1f]	9580	1			T1	6		T2	33		T3	12
valid_sources[0x20]	11088	1			T1	12		T2	49		T3	12
valid_sources[0x21]	7904	1			T1	26		T2	48		T3	16
valid_sources[0x22]	13663	1			T1	5		T2	57		T3	9
valid_sources[0x23]	7380	1			T1	39		T2	57		T3	17
valid_sources[0x24]	6889	1			T1	6		T2	44		T3	7
valid_sources[0x25]	23623	1			T1	15		T2	55		T3	6
valid_sources[0x26]	9577	1			T1	30		T2	52		T3	21
valid_sources[0x27]	17025	1			T1	18		T2	56		T3	9
valid_sources[0x28]	14061	1			T1	26		T2	63		T3	27
valid_sources[0x29]	7329	1			T1	52		T2	60		T3	40
valid_sources[0x2a]	6784	1			T1	12		T2	56		T3	10
valid_sources[0x2b]	7982	1			T1	19		T2	53		T3	8
valid_sources[0x2c]	8683	1			T1	22		T2	48		T3	10
valid_sources[0x2d]	11243	1			T1	11		T2	43		T3	16
valid_sources[0x2e]	7007	1			T1	6		T2	47		T3	4
valid_sources[0x2f]	12610	1			T1	1		T2	67		T3	17
valid_sources[0x30]	7495	1			T1	10		T2	44		T3	6
valid_sources[0x31]	6835	1			T1	24		T2	52		T3	26
valid_sources[0x32]	6569	1			T1	28		T2	39		T3	1
valid_sources[0x33]	8789	1			T1	12		T2	58		T3	6
valid_sources[0x34]	7044	1			T1	12		T2	56		T3	33
valid_sources[0x35]	7388	1			T1	17		T2	42		T3	8
valid_sources[0x36]	7091	1			T1	5		T2	27		T3	11
valid_sources[0x37]	11152	1			T1	19		T2	52		T3	21
valid_sources[0x38]	6556	1			T1	5		T2	31		T3	15
valid_sources[0x39]	7578	1			T1	31		T2	65		T3	6
valid_sources[0x3a]	6903	1			T1	42		T2	45		T3	7
valid_sources[0x3b]	9963	1			T1	12		T2	41		T3	7
valid_sources[0x3c]	6974	1			T1	27		T2	49		T3	8
valid_sources[0x3d]	7929	1			T1	50		T2	38		T3	7
valid_sources[0x3e]	10919	1			T1	23		T2	50		T3	47
valid_sources[0x3f]	17497	1			T1	41		T2	85		T3	6
valid_sources[0x40]	15502	1			T1	10		T2	41		T3	24
valid_sources[0x41]	10962	1			T2	46		T3	10		T4	12
valid_sources[0x42]	14219	1			T2	49		T3	5		T4	2
valid_sources[0x43]	6687	1			T1	16		T2	52		T3	12
valid_sources[0x44]	11507	1			T1	16		T2	32		T3	7
valid_sources[0x45]	7102	1			T1	25		T2	45		T3	16
valid_sources[0x46]	9065	1			T1	15		T2	47		T3	6
valid_sources[0x47]	9893	1			T1	29		T2	53		T3	12
valid_sources[0x48]	8161	1			T1	7		T2	56		T3	3
valid_sources[0x49]	7259	1			T1	44		T2	38		T3	13
valid_sources[0x4a]	7266	1			T1	10		T2	31		T3	5
valid_sources[0x4b]	8186	1			T1	7		T2	36		T3	14
valid_sources[0x4c]	6875	1			T1	16		T2	53		T3	19
valid_sources[0x4d]	7788	1			T1	10		T2	51		T3	39
valid_sources[0x4e]	11425	1			T1	4		T2	47		T3	22
valid_sources[0x4f]	7285	1			T1	12		T2	58		T3	6
valid_sources[0x50]	6992	1			T1	6		T2	45		T3	11
valid_sources[0x51]	6610	1			T1	15		T2	44		T3	3
valid_sources[0x52]	9315	1			T1	14		T2	56		T3	4
valid_sources[0x53]	13715	1			T1	30		T2	62		T3	32
valid_sources[0x54]	11759	1			T1	1		T2	39		T3	25
valid_sources[0x55]	7640	1			T1	3		T2	62		T3	6
valid_sources[0x56]	7068	1			T2	48		T3	15		T4	2
valid_sources[0x57]	13893	1			T1	7		T2	49		T3	7
valid_sources[0x58]	7442	1			T1	11		T2	60		T3	46
valid_sources[0x59]	6609	1			T1	22		T2	45		T3	19
valid_sources[0x5a]	12433	1			T1	13		T2	51		T3	13
valid_sources[0x5b]	10703	1			T1	2		T2	70		T3	12
valid_sources[0x5c]	8670	1			T1	1		T2	57		T3	20
valid_sources[0x5d]	9468	1			T2	44		T3	7		T4	10
valid_sources[0x5e]	7214	1			T1	16		T2	67		T3	12
valid_sources[0x5f]	8438	1			T1	22		T2	49		T3	12
valid_sources[0x60]	9844	1			T2	37		T3	6		T4	6
valid_sources[0x61]	11333	1			T1	12		T2	46		T3	51
valid_sources[0x62]	8169	1			T1	21		T2	50		T3	16
valid_sources[0x63]	10920	1			T1	10		T2	74		T3	2
valid_sources[0x64]	6418	1			T1	18		T2	50		T3	12
valid_sources[0x65]	11085	1			T1	11		T2	57		T3	9
valid_sources[0x66]	8635	1			T1	21		T2	52		T3	10
valid_sources[0x67]	11456	1			T1	9		T2	30		T3	9
valid_sources[0x68]	8433	1			T1	3		T2	66		T3	3
valid_sources[0x69]	6767	1			T1	30		T2	57		T3	5
valid_sources[0x6a]	23086	1			T1	21		T2	47		T3	10
valid_sources[0x6b]	8077	1			T1	30		T2	30		T3	12
valid_sources[0x6c]	10872	1			T1	6		T2	43		T3	21
valid_sources[0x6d]	8416	1			T1	5		T2	43		T3	18
valid_sources[0x6e]	6910	1			T1	53		T2	53		T3	15
valid_sources[0x6f]	9743	1			T1	5		T2	74		T3	9
valid_sources[0x70]	7814	1			T1	13		T2	50		T3	20
valid_sources[0x71]	6871	1			T1	5		T2	72		T3	24
valid_sources[0x72]	7332	1			T1	25		T2	48		T3	27
valid_sources[0x73]	6948	1			T1	26		T2	36		T3	8
valid_sources[0x74]	11567	1			T1	25		T2	54		T3	15
valid_sources[0x75]	7575	1			T1	34		T2	58		T3	14
valid_sources[0x76]	11391	1			T1	45		T2	59		T3	7
valid_sources[0x77]	9752	1			T1	3		T2	60		T3	19
valid_sources[0x78]	6825	1			T1	14		T2	50		T3	18
valid_sources[0x79]	6953	1			T1	23		T2	63		T3	3
valid_sources[0x7a]	7170	1			T1	30		T2	60		T3	9
valid_sources[0x7b]	7900	1			T1	9		T2	64		T3	16
valid_sources[0x7c]	7268	1			T1	26		T2	65		T3	64
valid_sources[0x7d]	12897	1			T1	8		T2	42		T3	10
valid_sources[0x7e]	20880	1			T1	10		T2	52		T3	2
valid_sources[0x7f]	15745	1			T1	5		T2	48		T3	20
valid_sources[0x80]	11188	1			T1	7		T2	55		T3	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1037292

1

T1

2004

T2

6183

T3

1327

values[0x0]

all_enables

biggest_size

80475

1

T1

51

T2

193

T3

263

values[0x1]

all_enables

biggest_size

58010

1

T1

41

T2

102

T3

174