Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31900	1			T1	9		T2	20		T3	187
auto[PWRUP]	132	1			T3	1		T29	1		T190	1
auto[ONEST_0]	63	1			T44	1		T23	1		T29	1
auto[ONEST_021]	12	1			T11	1		T130	1		T191	1
auto[ONEST_1]	91	1			T8	3		T44	1		T23	1
auto[ONEST_DONE]	10	1			T49	1		T192	1		T193	1
auto[LP_0]	157	1			T3	1		T8	1		T44	1
auto[LP_021]	27	1			T46	1		T12	1		T77	1
auto[LP_1]	131	1			T23	1		T29	3		T190	3
auto[LP_EVAL]	79	1			T8	1		T11	1		T23	1
auto[LP_SLP]	559	1			T3	9		T8	5		T44	10
auto[LP_PWRUP]	29	1			T8	1		T23	1		T46	2
auto[NP_0]	181	1			T8	3		T44	2		T23	1
auto[NP_021]	41	1			T8	1		T29	1		T49	1
auto[NP_1]	167	1			T3	1		T8	2		T44	2
auto[NP_EVAL]	36	1			T23	1		T130	1		T46	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

16

1

T29

1

T74

1

T194

1

min

31386

1

T1

9

T2

20

T3

184

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31397	1			T1	9		T2	20		T3	184
pow[0x1]	5	1			T86	1		T77	1		T195	1
pow[0x2]	22	1			T23	1		T130	2		T46	1
pow[0x3]	29	1			T46	1		T196	1		T31	1
pow[0x4]	60	1			T8	1		T23	1		T29	1
pow[0x5]	154	1			T8	3		T44	2		T23	2
pow[0x6]	282	1			T3	3		T8	2		T44	8
pow[0x7]	552	1			T3	6		T8	7		T44	16

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

220

1

T3

1

T8

4

T44

2

min

30865

1

T1

9

T2

20

T3

176

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30865	1			T1	9		T2	20		T3	176
pow[0x6]	3	1			T46	1		T197	1		T198	1
pow[0x7]	2	1			T199	1		T200	1		-	-
pow[0x8]	5	1			T201	1		T197	1		T202	1
pow[0x9]	9	1			T45	1		T203	1		T204	1
pow[0xa]	18	1			T130	1		T46	1		T196	1
pow[0xb]	36	1			T8	1		T23	2		T29	1
pow[0xc]	83	1			T8	1		T29	1		T190	1
pow[0xd]	160	1			T8	2		T44	5		T11	1
pow[0xe]	311	1			T3	5		T8	1		T44	6
pow[0xf]	643	1			T3	5		T8	4		T44	8