Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2402	1			T3	13		T8	15		T44	22
auto[PWRUP]	159	1			T3	2		T8	3		T44	2
auto[ONEST_0]	92	1			T44	2		T29	1		T190	1
auto[ONEST_021]	16	1			T45	1		T49	1		T77	1
auto[ONEST_1]	101	1			T3	3		T8	3		T29	3
auto[ONEST_DONE]	3	1			T44	1		T338	1		T339	1
auto[LP_0]	158	1			T3	1		T44	3		T23	1
auto[LP_021]	36	1			T44	2		T45	1		T74	1
auto[LP_1]	178	1			T8	2		T44	3		T29	2
auto[LP_EVAL]	68	1			T8	1		T11	1		T23	2
auto[LP_SLP]	564	1			T3	3		T8	5		T44	6
auto[LP_PWRUP]	33	1			T8	1		T44	1		T49	1
auto[NP_0]	250	1			T3	4		T8	2		T44	3
auto[NP_021]	56	1			T8	2		T44	1		T29	1
auto[NP_1]	220	1			T3	6		T8	1		T44	4
auto[NP_EVAL]	27	1			T11	1		T29	1		T45	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T3

1

T201

1

T340

1

min

2031

1

T3

8

T8

6

T44

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2045	1			T3	8		T8	6		T44	10
pow[0x1]	10	1			T46	2		T12	1		T191	1
pow[0x2]	23	1			T8	1		T130	1		T48	2
pow[0x3]	46	1			T23	1		T45	1		T196	1
pow[0x4]	72	1			T8	1		T44	1		T29	1
pow[0x5]	156	1			T3	1		T8	2		T44	4
pow[0x6]	305	1			T3	4		T8	4		T44	7
pow[0x7]	597	1			T3	5		T8	7		T44	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T3

1

T8

1

T44

5

min

1385

1

T3

11

T8

1

T44

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1394	1			T3	11		T8	1		T44	2
pow[0x1]	13	1			T23	1		T221	1		T217	1
pow[0x2]	26	1			T11	1		T33	1		T16	1
pow[0x3]	39	1			T11	2		T33	2		T12	2
pow[0x4]	55	1			T11	3		T13	1		T14	2
pow[0x7]	6	1			T11	1		T45	1		T191	1
pow[0x8]	6	1			T196	1		T48	2		T193	1
pow[0x9]	8	1			T193	1		T201	1		T221	1
pow[0xa]	17	1			T8	1		T45	1		T46	3
pow[0xb]	48	1			T8	1		T23	1		T29	1
pow[0xc]	61	1			T3	3		T29	2		T190	1
pow[0xd]	164	1			T3	1		T8	1		T44	5
pow[0xe]	332	1			T3	2		T8	5		T44	10
pow[0xf]	625	1			T3	7		T8	10		T44	8