Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : adc_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.00 96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.adc_ctrl_csr_assert 96.00 96.00



Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.00 96.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.00 96.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : adc_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 25 25 100.00 24 96.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 25 25 100.00 24 96.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 2147483647 0 0 0
adc_chn0_filter_ctl_0_rd_A 2147483647 1494 0 0
adc_chn0_filter_ctl_1_rd_A 2147483647 1551 0 0
adc_chn0_filter_ctl_2_rd_A 2147483647 1599 0 0
adc_chn0_filter_ctl_3_rd_A 2147483647 1470 0 0
adc_chn0_filter_ctl_4_rd_A 2147483647 1444 0 0
adc_chn0_filter_ctl_5_rd_A 2147483647 1358 0 0
adc_chn0_filter_ctl_6_rd_A 2147483647 1404 0 0
adc_chn0_filter_ctl_7_rd_A 2147483647 1608 0 0
adc_chn1_filter_ctl_0_rd_A 2147483647 1465 0 0
adc_chn1_filter_ctl_1_rd_A 2147483647 1381 0 0
adc_chn1_filter_ctl_2_rd_A 2147483647 1584 0 0
adc_chn1_filter_ctl_3_rd_A 2147483647 1454 0 0
adc_chn1_filter_ctl_4_rd_A 2147483647 1505 0 0
adc_chn1_filter_ctl_5_rd_A 2147483647 1509 0 0
adc_chn1_filter_ctl_6_rd_A 2147483647 1454 0 0
adc_chn1_filter_ctl_7_rd_A 2147483647 1481 0 0
adc_en_ctl_rd_A 2147483647 1244 0 0
adc_fsm_rst_rd_A 2147483647 1122 0 0
adc_intr_ctl_rd_A 2147483647 1574 0 0
adc_lp_sample_ctl_rd_A 2147483647 1085 0 0
adc_pd_ctl_rd_A 2147483647 1482 0 0
adc_sample_ctl_rd_A 2147483647 1192 0 0
adc_wakeup_ctl_rd_A 2147483647 1150 0 0
intr_enable_rd_A 2147483647 1679 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 0 0 0

adc_chn0_filter_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1494 0 0
T11 636291 25 0 0
T12 0 12 0 0
T13 0 24 0 0
T14 0 21 0 0
T15 0 6 0 0
T16 0 15 0 0
T17 0 22 0 0
T18 0 30 0 0
T19 0 40 0 0
T20 0 1 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn0_filter_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1551 0 0
T11 636291 35 0 0
T12 0 13 0 0
T13 0 24 0 0
T14 0 34 0 0
T15 0 4 0 0
T16 0 14 0 0
T17 0 15 0 0
T18 0 18 0 0
T19 0 43 0 0
T20 0 6 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn0_filter_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1599 0 0
T11 636291 47 0 0
T12 0 14 0 0
T13 0 27 0 0
T14 0 34 0 0
T15 0 10 0 0
T16 0 26 0 0
T17 0 11 0 0
T18 0 11 0 0
T19 0 40 0 0
T20 0 13 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn0_filter_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1470 0 0
T11 636291 24 0 0
T12 0 21 0 0
T13 0 10 0 0
T14 0 46 0 0
T15 0 7 0 0
T16 0 28 0 0
T17 0 21 0 0
T18 0 19 0 0
T19 0 35 0 0
T20 0 10 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn0_filter_ctl_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1444 0 0
T11 636291 43 0 0
T12 0 15 0 0
T13 0 11 0 0
T14 0 32 0 0
T15 0 8 0 0
T16 0 16 0 0
T17 0 18 0 0
T18 0 5 0 0
T19 0 34 0 0
T20 0 23 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn0_filter_ctl_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1358 0 0
T11 636291 45 0 0
T12 0 15 0 0
T13 0 4 0 0
T14 0 12 0 0
T15 0 2 0 0
T16 0 16 0 0
T17 0 21 0 0
T18 0 27 0 0
T19 0 28 0 0
T20 0 13 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn0_filter_ctl_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1404 0 0
T11 636291 12 0 0
T12 0 3 0 0
T13 0 10 0 0
T14 0 22 0 0
T15 0 9 0 0
T16 0 20 0 0
T17 0 24 0 0
T18 0 11 0 0
T19 0 44 0 0
T20 0 16 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn0_filter_ctl_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1608 0 0
T11 636291 25 0 0
T12 0 6 0 0
T13 0 8 0 0
T14 0 19 0 0
T15 0 8 0 0
T16 0 30 0 0
T17 0 25 0 0
T18 0 17 0 0
T19 0 41 0 0
T20 0 15 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn1_filter_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1465 0 0
T11 636291 28 0 0
T12 0 13 0 0
T13 0 7 0 0
T14 0 25 0 0
T15 0 12 0 0
T16 0 24 0 0
T17 0 24 0 0
T18 0 15 0 0
T19 0 38 0 0
T20 0 10 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn1_filter_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1381 0 0
T11 636291 40 0 0
T12 0 11 0 0
T13 0 24 0 0
T14 0 8 0 0
T15 0 5 0 0
T16 0 25 0 0
T17 0 11 0 0
T18 0 20 0 0
T19 0 36 0 0
T20 0 12 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn1_filter_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1584 0 0
T11 636291 35 0 0
T12 0 5 0 0
T13 0 15 0 0
T14 0 15 0 0
T15 0 9 0 0
T16 0 22 0 0
T17 0 24 0 0
T18 0 18 0 0
T19 0 41 0 0
T20 0 9 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn1_filter_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1454 0 0
T11 636291 31 0 0
T12 0 8 0 0
T13 0 14 0 0
T14 0 14 0 0
T15 0 5 0 0
T16 0 21 0 0
T17 0 8 0 0
T18 0 13 0 0
T19 0 46 0 0
T20 0 14 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn1_filter_ctl_4_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1505 0 0
T11 636291 27 0 0
T12 0 10 0 0
T13 0 17 0 0
T14 0 16 0 0
T15 0 6 0 0
T16 0 8 0 0
T17 0 19 0 0
T18 0 20 0 0
T19 0 40 0 0
T20 0 24 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn1_filter_ctl_5_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1509 0 0
T11 636291 41 0 0
T12 0 14 0 0
T13 0 18 0 0
T14 0 20 0 0
T15 0 9 0 0
T16 0 6 0 0
T17 0 22 0 0
T18 0 17 0 0
T19 0 47 0 0
T20 0 5 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn1_filter_ctl_6_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1454 0 0
T11 636291 29 0 0
T12 0 19 0 0
T13 0 22 0 0
T14 0 23 0 0
T15 0 10 0 0
T16 0 28 0 0
T17 0 8 0 0
T18 0 22 0 0
T19 0 35 0 0
T20 0 6 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_chn1_filter_ctl_7_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1481 0 0
T11 636291 20 0 0
T12 0 9 0 0
T13 0 2 0 0
T14 0 18 0 0
T15 0 23 0 0
T16 0 29 0 0
T17 0 18 0 0
T18 0 27 0 0
T19 0 42 0 0
T20 0 9 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_en_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1244 0 0
T11 636291 49 0 0
T12 0 12 0 0
T13 0 13 0 0
T14 0 17 0 0
T15 0 1 0 0
T16 0 23 0 0
T17 0 23 0 0
T18 0 15 0 0
T19 0 19 0 0
T20 0 12 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_fsm_rst_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1122 0 0
T11 636291 37 0 0
T12 0 9 0 0
T13 0 9 0 0
T14 0 24 0 0
T15 0 20 0 0
T16 0 17 0 0
T17 0 10 0 0
T18 0 11 0 0
T19 0 37 0 0
T20 0 11 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1574 0 0
T11 636291 35 0 0
T12 0 17 0 0
T13 0 4 0 0
T14 0 16 0 0
T15 0 14 0 0
T16 0 12 0 0
T17 0 23 0 0
T18 0 19 0 0
T19 0 41 0 0
T20 0 13 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_lp_sample_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1085 0 0
T11 636291 46 0 0
T12 0 13 0 0
T13 0 16 0 0
T14 0 29 0 0
T15 0 2 0 0
T16 0 22 0 0
T17 0 22 0 0
T18 0 23 0 0
T19 0 40 0 0
T20 0 15 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_pd_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1482 0 0
T11 636291 33 0 0
T12 0 10 0 0
T13 0 16 0 0
T14 0 12 0 0
T15 0 7 0 0
T16 0 22 0 0
T17 0 21 0 0
T18 0 7 0 0
T19 0 39 0 0
T20 0 12 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_sample_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1192 0 0
T11 636291 39 0 0
T12 0 12 0 0
T13 0 6 0 0
T14 0 20 0 0
T15 0 5 0 0
T16 0 32 0 0
T17 0 31 0 0
T18 0 16 0 0
T19 0 22 0 0
T20 0 17 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

adc_wakeup_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1150 0 0
T11 636291 45 0 0
T12 0 13 0 0
T13 0 8 0 0
T14 0 15 0 0
T15 0 1 0 0
T16 0 31 0 0
T17 0 19 0 0
T18 0 20 0 0
T19 0 44 0 0
T20 0 14 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1679 0 0
T11 636291 29 0 0
T12 0 41 0 0
T13 0 20 0 0
T14 0 58 0 0
T15 0 9 0 0
T16 0 25 0 0
T17 0 31 0 0
T21 297681 0 0 0
T22 166173 0 0 0
T23 912544 0 0 0
T24 312913 0 0 0
T25 105454 0 0 0
T26 111826 0 0 0
T27 24282 0 0 0
T28 158873 0 0 0
T29 255519 0 0 0
T30 0 26 0 0
T31 0 21 0 0
T32 0 11 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%