Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1190493

1

T1

38

T2

2159

T3

6277

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2113623	1			T2	3897		T3	11974		T4	1676
values[0x0]	145526	1			T1	31		T2	216		T3	337
values[0x1]	145436	1			T1	30		T2	202		T3	347

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	972666	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1431919

1

T1

44

T2

2579

T3

7593

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7947	1			T2	9		T3	25		T4	9
valid_sources[0x01]	6831	1			T2	8		T3	24		T4	11
valid_sources[0x02]	10033	1			T1	1		T2	2765		T3	24
valid_sources[0x03]	7209	1			T1	1		T2	5		T3	25
valid_sources[0x04]	6642	1			T1	1		T2	2		T3	46
valid_sources[0x05]	8623	1			T2	3		T3	49		T4	12
valid_sources[0x06]	15148	1			T2	4		T3	11		T4	6
valid_sources[0x07]	7051	1			T1	1		T2	2		T3	41
valid_sources[0x08]	8256	1			T2	5		T3	59		T4	4
valid_sources[0x09]	8417	1			T2	5		T3	45		T4	9
valid_sources[0x0a]	7421	1			T2	5		T3	32		T4	7
valid_sources[0x0b]	7692	1			T2	5		T3	32		T4	10
valid_sources[0x0c]	13003	1			T2	8		T3	4262		T4	7
valid_sources[0x0d]	7447	1			T2	4		T3	34		T4	6
valid_sources[0x0e]	10196	1			T2	5		T3	25		T4	4
valid_sources[0x0f]	7039	1			T2	8		T3	51		T4	7
valid_sources[0x10]	7033	1			T2	5		T3	34		T4	9
valid_sources[0x11]	7013	1			T2	7		T3	35		T4	10
valid_sources[0x12]	7927	1			T2	11		T3	30		T4	6
valid_sources[0x13]	8209	1			T1	1		T2	1		T3	44
valid_sources[0x14]	7790	1			T2	5		T3	36		T4	7
valid_sources[0x15]	12952	1			T2	7		T3	43		T4	2
valid_sources[0x16]	7238	1			T2	7		T3	27		T4	7
valid_sources[0x17]	13736	1			T2	7		T3	32		T4	8
valid_sources[0x18]	7162	1			T2	6		T3	44		T4	10
valid_sources[0x19]	10075	1			T2	8		T3	23		T4	12
valid_sources[0x1a]	8941	1			T2	5		T3	48		T4	14
valid_sources[0x1b]	14661	1			T2	7		T3	29		T4	5
valid_sources[0x1c]	7121	1			T1	3		T2	2		T3	37
valid_sources[0x1d]	7527	1			T2	5		T3	24		T4	10
valid_sources[0x1e]	10948	1			T2	4		T3	18		T4	5
valid_sources[0x1f]	7254	1			T2	13		T3	21		T4	6
valid_sources[0x20]	7053	1			T2	9		T3	26		T4	12
valid_sources[0x21]	7055	1			T2	10		T3	20		T4	6
valid_sources[0x22]	11241	1			T2	7		T3	23		T4	7
valid_sources[0x23]	7304	1			T2	4		T3	38		T4	7
valid_sources[0x24]	11625	1			T2	5		T3	34		T4	7
valid_sources[0x25]	8151	1			T2	6		T3	35		T4	7
valid_sources[0x26]	7270	1			T2	10		T3	26		T4	6
valid_sources[0x27]	7189	1			T1	1		T2	10		T3	46
valid_sources[0x28]	11548	1			T2	7		T3	29		T4	6
valid_sources[0x29]	8251	1			T1	1		T2	5		T3	57
valid_sources[0x2a]	7403	1			T2	3		T3	27		T4	13
valid_sources[0x2b]	8588	1			T2	2		T3	55		T4	11
valid_sources[0x2c]	7760	1			T2	2		T3	36		T4	6
valid_sources[0x2d]	7133	1			T1	1		T2	3		T3	51
valid_sources[0x2e]	7039	1			T2	7		T3	22		T4	10
valid_sources[0x2f]	9855	1			T2	5		T3	28		T4	4
valid_sources[0x30]	7453	1			T2	7		T3	22		T4	9
valid_sources[0x31]	7773	1			T2	10		T3	35		T4	6
valid_sources[0x32]	7546	1			T2	2		T3	37		T4	9
valid_sources[0x33]	16061	1			T1	1		T2	4		T3	38
valid_sources[0x34]	7373	1			T2	13		T3	26		T4	6
valid_sources[0x35]	8826	1			T2	2		T3	18		T4	10
valid_sources[0x36]	7045	1			T1	1		T2	7		T3	20
valid_sources[0x37]	8160	1			T2	7		T3	39		T4	10
valid_sources[0x38]	10644	1			T2	7		T3	21		T4	3
valid_sources[0x39]	8176	1			T1	4		T2	6		T3	40
valid_sources[0x3a]	11296	1			T2	8		T3	35		T4	8
valid_sources[0x3b]	7233	1			T2	3		T3	36		T4	9
valid_sources[0x3c]	11529	1			T2	6		T3	14		T4	11
valid_sources[0x3d]	7937	1			T1	1		T2	3		T3	27
valid_sources[0x3e]	11013	1			T2	7		T3	18		T4	9
valid_sources[0x3f]	7128	1			T2	7		T3	17		T4	7
valid_sources[0x40]	7128	1			T2	10		T3	21		T4	9
valid_sources[0x41]	12323	1			T2	5		T3	19		T4	9
valid_sources[0x42]	7040	1			T2	8		T3	32		T4	5
valid_sources[0x43]	11245	1			T2	9		T3	31		T4	8
valid_sources[0x44]	7043	1			T2	8		T3	36		T4	6
valid_sources[0x45]	24280	1			T2	3		T3	44		T4	5
valid_sources[0x46]	8281	1			T2	4		T3	19		T4	8
valid_sources[0x47]	7371	1			T1	2		T2	2		T3	11
valid_sources[0x48]	11406	1			T2	4		T3	33		T4	4
valid_sources[0x49]	7262	1			T1	1		T2	3		T3	25
valid_sources[0x4a]	16439	1			T2	11		T3	38		T4	14
valid_sources[0x4b]	11564	1			T2	5		T3	34		T4	2
valid_sources[0x4c]	7613	1			T2	6		T3	40		T4	9
valid_sources[0x4d]	7144	1			T1	1		T2	5		T3	43
valid_sources[0x4e]	10662	1			T2	4		T3	28		T4	5
valid_sources[0x4f]	12497	1			T2	1		T3	23		T4	8
valid_sources[0x50]	8402	1			T2	7		T3	45		T4	7
valid_sources[0x51]	7658	1			T2	5		T3	69		T4	6
valid_sources[0x52]	8382	1			T2	6		T3	40		T4	9
valid_sources[0x53]	20254	1			T2	15		T3	22		T4	5
valid_sources[0x54]	10678	1			T2	5		T3	17		T4	2
valid_sources[0x55]	7131	1			T2	7		T3	32		T4	8
valid_sources[0x56]	7492	1			T1	1		T2	9		T3	19
valid_sources[0x57]	7229	1			T2	9		T3	45		T4	7
valid_sources[0x58]	7936	1			T2	1		T3	16		T4	1
valid_sources[0x59]	7117	1			T2	5		T3	33		T4	14
valid_sources[0x5a]	8386	1			T2	5		T3	41		T4	2
valid_sources[0x5b]	6930	1			T2	2		T3	39		T4	6
valid_sources[0x5c]	8870	1			T2	13		T3	8		T4	7
valid_sources[0x5d]	8949	1			T1	3		T2	9		T3	51
valid_sources[0x5e]	15602	1			T1	1		T2	6		T3	44
valid_sources[0x5f]	8688	1			T2	7		T3	19		T4	10
valid_sources[0x60]	7393	1			T1	1		T2	6		T3	29
valid_sources[0x61]	9852	1			T2	3		T3	31		T4	9
valid_sources[0x62]	7230	1			T2	10		T3	44		T4	9
valid_sources[0x63]	7161	1			T2	6		T3	34		T4	3
valid_sources[0x64]	9838	1			T2	9		T3	27		T4	3
valid_sources[0x65]	7841	1			T1	1		T2	3		T3	42
valid_sources[0x66]	6902	1			T2	6		T3	39		T4	13
valid_sources[0x67]	6639	1			T2	8		T3	14		T4	6
valid_sources[0x68]	7081	1			T2	8		T3	37		T4	8
valid_sources[0x69]	7542	1			T2	11		T3	47		T4	2
valid_sources[0x6a]	7051	1			T2	6		T3	25		T4	4
valid_sources[0x6b]	7140	1			T2	3		T3	20		T4	7
valid_sources[0x6c]	7290	1			T2	5		T3	31		T4	6
valid_sources[0x6d]	8364	1			T2	6		T3	82		T4	12
valid_sources[0x6e]	8735	1			T2	8		T3	31		T4	8
valid_sources[0x6f]	7306	1			T2	10		T3	25		T4	10
valid_sources[0x70]	7000	1			T1	1		T2	4		T3	27
valid_sources[0x71]	11509	1			T2	5		T3	25		T4	10
valid_sources[0x72]	7215	1			T2	8		T3	34		T4	3
valid_sources[0x73]	8164	1			T1	1		T2	9		T3	38
valid_sources[0x74]	6724	1			T2	7		T3	21		T4	6
valid_sources[0x75]	9749	1			T2	9		T3	25		T4	4
valid_sources[0x76]	10619	1			T2	8		T3	15		T4	2
valid_sources[0x77]	9964	1			T2	7		T3	56		T4	12
valid_sources[0x78]	11324	1			T2	6		T3	16		T4	9
valid_sources[0x79]	9161	1			T2	6		T3	38		T4	5
valid_sources[0x7a]	7265	1			T2	7		T3	16		T4	10
valid_sources[0x7b]	9447	1			T2	9		T3	37		T4	8
valid_sources[0x7c]	7270	1			T2	6		T3	52		T4	5
valid_sources[0x7d]	7124	1			T2	8		T3	34		T4	4
valid_sources[0x7e]	13889	1			T2	3		T3	38		T4	4
valid_sources[0x7f]	11212	1			T2	5		T3	49		T4	7
valid_sources[0x80]	7120	1			T2	6		T3	36		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1052903

1

T2

1988

T3

6002

T4

852

values[0x0]

all_enables

biggest_size

79972

1

T1

24

T2

114

T3

176

values[0x1]

all_enables

biggest_size

57618

1

T1

14

T2

57

T3

99