Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	25925	1			T2	11		T3	27		T4	19
auto[PWRUP]	99	1			T6	1		T13	1		T32	2
auto[ONEST_0]	66	1			T6	1		T32	1		T45	1
auto[ONEST_021]	7	1			T33	1		T40	1		T194	1
auto[ONEST_1]	74	1			T6	2		T13	2		T32	1
auto[ONEST_DONE]	3	1			T40	1		T98	1		T195	1
auto[LP_0]	103	1			T6	1		T13	4		T32	4
auto[LP_021]	27	1			T44	1		T40	1		T196	1
auto[LP_1]	114	1			T6	1		T13	4		T32	1
auto[LP_EVAL]	66	1			T13	2		T45	1		T37	1
auto[LP_SLP]	447	1			T6	4		T13	3		T32	5
auto[LP_PWRUP]	27	1			T45	1		T33	1		T44	1
auto[NP_0]	134	1			T6	1		T13	1		T32	3
auto[NP_021]	30	1			T32	1		T45	1		T38	1
auto[NP_1]	126	1			T32	2		T45	3		T38	2
auto[NP_EVAL]	30	1			T39	1		T44	1		T40	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T39

1

T197

1

T198

1

min

25497

1

T2

11

T3

27

T4

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25508	1			T2	11		T3	27		T4	19
pow[0x1]	7	1			T45	1		T197	1		T199	1
pow[0x2]	13	1			T6	1		T45	1		T40	1
pow[0x3]	21	1			T32	2		T33	1		T44	2
pow[0x4]	67	1			T13	2		T39	1		T33	1
pow[0x5]	112	1			T13	1		T32	1		T45	5
pow[0x6]	211	1			T6	4		T13	5		T32	2
pow[0x7]	471	1			T6	5		T13	6		T32	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

181

1

T6

1

T13

3

T32

1

min

25047

1

T2

11

T3

27

T4

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25047	1			T2	11		T3	27		T4	19
pow[0x5]	1	1			T200	1		-	-		-	-
pow[0x6]	1	1			T198	1		-	-		-	-
pow[0x8]	5	1			T38	1		T22	1		T201	1
pow[0x9]	5	1			T44	1		T202	1		T203	2
pow[0xa]	15	1			T32	1		T39	1		T196	1
pow[0xb]	34	1			T13	1		T33	1		T196	2
pow[0xc]	52	1			T39	1		T33	1		T44	2
pow[0xd]	126	1			T6	3		T13	4		T32	2
pow[0xe]	248	1			T6	1		T13	2		T32	2
pow[0xf]	501	1			T6	10		T13	5		T32	6