Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2126	1			T6	19		T13	17		T14	12
auto[PWRUP]	123	1			T32	3		T45	3		T37	1
auto[ONEST_0]	63	1			T13	1		T14	1		T15	1
auto[ONEST_021]	18	1			T6	1		T15	1		T194	1
auto[ONEST_1]	73	1			T13	1		T14	1		T32	1
auto[ONEST_DONE]	4	1			T355	1		T356	1		T357	1
auto[LP_0]	124	1			T6	1		T13	3		T14	1
auto[LP_021]	27	1			T6	1		T13	1		T44	1
auto[LP_1]	108	1			T6	1		T13	1		T45	4
auto[LP_EVAL]	47	1			T32	1		T45	2		T39	2
auto[LP_SLP]	469	1			T6	4		T13	10		T14	1
auto[LP_PWRUP]	32	1			T32	1		T45	1		T44	1
auto[NP_0]	195	1			T6	2		T13	4		T32	1
auto[NP_021]	42	1			T6	1		T45	1		T38	1
auto[NP_1]	216	1			T6	1		T13	1		T14	2
auto[NP_EVAL]	24	1			T13	1		T15	2		T38	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T13

1

T358

1

T359

1

min

1888

1

T6

19

T13

12

T14

17

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1902	1			T6	19		T13	12		T14	17
pow[0x1]	9	1			T360	1		T361	1		T201	2
pow[0x2]	18	1			T14	1		T39	1		T44	1
pow[0x3]	28	1			T45	1		T196	1		T362	1
pow[0x4]	60	1			T32	2		T45	1		T38	1
pow[0x5]	127	1			T6	2		T13	4		T32	2
pow[0x6]	224	1			T6	4		T32	3		T45	6
pow[0x7]	434	1			T6	3		T13	9		T32	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

166

1

T13

2

T32

6

T45

4

min

1334

1

T6

15

T13

4

T14

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1338	1			T6	15		T13	4		T14	16
pow[0x1]	18	1			T41	1		T363	1		T214	1
pow[0x2]	21	1			T38	3		T41	1		T17	1
pow[0x3]	40	1			T6	3		T15	1		T37	2
pow[0x4]	66	1			T14	2		T15	5		T38	3
pow[0x7]	1	1			T364	1		-	-		-	-
pow[0x8]	3	1			T33	1		T358	1		T365	1
pow[0x9]	14	1			T32	1		T46	1		T44	1
pow[0xa]	16	1			T45	1		T46	1		T194	1
pow[0xb]	28	1			T6	1		T13	1		T38	1
pow[0xc]	70	1			T13	2		T32	1		T45	2
pow[0xd]	135	1			T6	1		T13	3		T32	2
pow[0xe]	266	1			T6	4		T13	3		T32	6
pow[0xf]	508	1			T6	3		T13	9		T32	8