Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2108	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1970	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1855	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1950	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1948	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2029	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1831	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2008	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1829	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1908	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2031	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2019	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2033	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2044	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2008	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2050	0	0
adc_en_ctl_rd_A	2147483647	1661	0	0
adc_fsm_rst_rd_A	2147483647	1844	0	0
adc_intr_ctl_rd_A	2147483647	2113	0	0
adc_lp_sample_ctl_rd_A	2147483647	1585	0	0
adc_pd_ctl_rd_A	2147483647	1840	0	0
adc_sample_ctl_rd_A	2147483647	1570	0	0
adc_wakeup_ctl_rd_A	2147483647	1591	0	0
intr_enable_rd_A	2147483647	2541	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2108	0	0
T14	524196	42	0	0
T15	0	34	0	0
T16	0	26	0	0
T17	0	26	0	0
T18	0	11	0	0
T19	0	16	0	0
T20	0	54	0	0
T21	0	18	0	0
T22	0	30	0	0
T23	0	28	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1970	0	0
T14	524196	17	0	0
T15	0	38	0	0
T16	0	14	0	0
T17	0	10	0	0
T18	0	13	0	0
T19	0	20	0	0
T20	0	36	0	0
T21	0	16	0	0
T22	0	28	0	0
T23	0	41	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1855	0	0
T14	524196	14	0	0
T15	0	43	0	0
T16	0	30	0	0
T17	0	15	0	0
T18	0	11	0	0
T19	0	21	0	0
T20	0	46	0	0
T21	0	16	0	0
T22	0	20	0	0
T23	0	27	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1950	0	0
T14	524196	29	0	0
T15	0	45	0	0
T16	0	11	0	0
T17	0	17	0	0
T18	0	22	0	0
T19	0	17	0	0
T20	0	39	0	0
T21	0	15	0	0
T22	0	22	0	0
T23	0	40	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1948	0	0
T14	524196	15	0	0
T15	0	49	0	0
T16	0	18	0	0
T17	0	27	0	0
T18	0	6	0	0
T19	0	35	0	0
T20	0	36	0	0
T21	0	16	0	0
T22	0	25	0	0
T23	0	37	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2029	0	0
T14	524196	15	0	0
T15	0	42	0	0
T16	0	20	0	0
T17	0	13	0	0
T18	0	18	0	0
T19	0	31	0	0
T20	0	50	0	0
T21	0	30	0	0
T22	0	23	0	0
T23	0	37	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1831	0	0
T14	524196	13	0	0
T15	0	39	0	0
T16	0	22	0	0
T17	0	22	0	0
T18	0	24	0	0
T19	0	20	0	0
T20	0	31	0	0
T21	0	15	0	0
T22	0	15	0	0
T23	0	24	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2008	0	0
T14	524196	31	0	0
T15	0	38	0	0
T16	0	27	0	0
T17	0	14	0	0
T18	0	14	0	0
T19	0	17	0	0
T20	0	42	0	0
T21	0	24	0	0
T22	0	27	0	0
T23	0	40	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1829	0	0
T14	524196	14	0	0
T15	0	36	0	0
T16	0	26	0	0
T17	0	19	0	0
T18	0	15	0	0
T19	0	21	0	0
T20	0	47	0	0
T21	0	19	0	0
T22	0	25	0	0
T23	0	39	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1908	0	0
T14	524196	6	0	0
T15	0	31	0	0
T16	0	33	0	0
T17	0	16	0	0
T18	0	15	0	0
T19	0	24	0	0
T20	0	45	0	0
T21	0	13	0	0
T22	0	23	0	0
T23	0	40	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2031	0	0
T14	524196	14	0	0
T15	0	31	0	0
T16	0	12	0	0
T17	0	11	0	0
T18	0	23	0	0
T19	0	21	0	0
T20	0	34	0	0
T21	0	21	0	0
T22	0	46	0	0
T23	0	41	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2019	0	0
T14	524196	11	0	0
T15	0	43	0	0
T16	0	22	0	0
T17	0	27	0	0
T18	0	23	0	0
T19	0	15	0	0
T20	0	34	0	0
T21	0	13	0	0
T22	0	23	0	0
T23	0	53	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2033	0	0
T14	524196	11	0	0
T15	0	24	0	0
T16	0	13	0	0
T17	0	18	0	0
T18	0	13	0	0
T19	0	23	0	0
T20	0	30	0	0
T21	0	18	0	0
T22	0	35	0	0
T23	0	33	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2044	0	0
T14	524196	14	0	0
T15	0	46	0	0
T16	0	9	0	0
T17	0	13	0	0
T18	0	19	0	0
T19	0	16	0	0
T20	0	55	0	0
T21	0	10	0	0
T22	0	34	0	0
T23	0	40	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2008	0	0
T14	524196	10	0	0
T15	0	43	0	0
T16	0	29	0	0
T17	0	32	0	0
T18	0	26	0	0
T19	0	16	0	0
T20	0	50	0	0
T21	0	11	0	0
T22	0	30	0	0
T23	0	39	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2050	0	0
T14	524196	10	0	0
T15	0	35	0	0
T16	0	27	0	0
T17	0	16	0	0
T18	0	24	0	0
T19	0	14	0	0
T20	0	45	0	0
T21	0	25	0	0
T22	0	31	0	0
T23	0	30	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1661	0	0
T14	524196	25	0	0
T15	0	40	0	0
T16	0	30	0	0
T17	0	20	0	0
T18	0	20	0	0
T19	0	14	0	0
T20	0	41	0	0
T21	0	16	0	0
T22	0	35	0	0
T23	0	55	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1844	0	0
T14	524196	30	0	0
T15	0	33	0	0
T16	0	16	0	0
T17	0	10	0	0
T18	0	10	0	0
T19	0	24	0	0
T20	0	37	0	0
T21	0	21	0	0
T22	0	44	0	0
T23	0	36	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2113	0	0
T14	524196	8	0	0
T15	0	29	0	0
T16	0	18	0	0
T17	0	18	0	0
T18	0	28	0	0
T19	0	8	0	0
T20	0	37	0	0
T21	0	16	0	0
T22	0	45	0	0
T23	0	39	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1585	0	0
T14	524196	8	0	0
T15	0	31	0	0
T16	0	22	0	0
T17	0	20	0	0
T18	0	11	0	0
T19	0	11	0	0
T20	0	46	0	0
T21	0	3	0	0
T22	0	46	0	0
T23	0	32	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1840	0	0
T14	524196	33	0	0
T15	0	48	0	0
T16	0	27	0	0
T17	0	15	0	0
T18	0	23	0	0
T19	0	24	0	0
T20	0	32	0	0
T21	0	18	0	0
T22	0	14	0	0
T23	0	30	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1570	0	0
T14	524196	23	0	0
T15	0	45	0	0
T16	0	8	0	0
T17	0	18	0	0
T18	0	18	0	0
T19	0	21	0	0
T20	0	44	0	0
T21	0	9	0	0
T22	0	24	0	0
T23	0	17	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1591	0	0
T14	524196	10	0	0
T15	0	22	0	0
T16	0	13	0	0
T17	0	27	0	0
T18	0	14	0	0
T19	0	14	0	0
T20	0	26	0	0
T21	0	9	0	0
T22	0	30	0	0
T23	0	44	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2541	0	0
T14	524196	32	0	0
T15	0	75	0	0
T16	0	38	0	0
T17	0	33	0	0
T18	0	37	0	0
T19	0	53	0	0
T24	164396	0	0	0
T25	145539	0	0	0
T26	346210	0	0	0
T27	213276	0	0	0
T28	126836	0	0	0
T29	133152	0	0	0
T30	105249	0	0	0
T31	489682	0	0	0
T32	189259	0	0	0
T33	0	20	0	0
T34	0	17	0	0
T35	0	21	0	0
T36	0	16	0	0