Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1142817	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1117343

1

T1

1059

T2

6379

T3

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1976442	1			T1	1974		T2	12139		T4	81
values[0x0]	141298	1			T1	139		T2	335		T3	25
values[0x1]	142420	1			T1	134		T2	379		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	915425	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1344735

1

T1

1288

T2

7630

T3

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7944	1			T1	5		T2	31		T5	6
valid_sources[0x01]	8314	1			T1	8		T2	40		T5	1
valid_sources[0x02]	11629	1			T1	11		T2	29		T5	1
valid_sources[0x03]	7671	1			T1	8		T2	32		T4	1
valid_sources[0x04]	7376	1			T1	3		T2	33		T5	3
valid_sources[0x05]	11329	1			T1	2		T2	28		T5	2
valid_sources[0x06]	7796	1			T1	5		T2	28		T5	10
valid_sources[0x07]	12067	1			T1	3		T2	26		T4	1
valid_sources[0x08]	6854	1			T1	9		T2	29		T5	2
valid_sources[0x09]	8120	1			T1	22		T2	35		T5	2
valid_sources[0x0a]	6821	1			T2	30		T5	5		T7	43
valid_sources[0x0b]	6889	1			T1	6		T2	24		T5	1
valid_sources[0x0c]	15738	1			T1	4		T2	30		T4	3
valid_sources[0x0d]	6981	1			T1	6		T2	31		T4	2
valid_sources[0x0e]	6692	1			T1	14		T2	34		T5	6
valid_sources[0x0f]	9167	1			T1	10		T2	26		T3	6
valid_sources[0x10]	12372	1			T1	15		T2	27		T5	3
valid_sources[0x11]	6730	1			T1	9		T2	28		T5	2
valid_sources[0x12]	7028	1			T1	14		T2	21		T5	3
valid_sources[0x13]	9582	1			T1	23		T2	28		T5	1
valid_sources[0x14]	6730	1			T1	2		T2	46		T7	40
valid_sources[0x15]	8196	1			T1	3		T2	36		T5	4
valid_sources[0x16]	6974	1			T1	6		T2	34		T5	3
valid_sources[0x17]	7374	1			T1	18		T2	27		T4	2
valid_sources[0x18]	6802	1			T2	36		T4	1		T5	5
valid_sources[0x19]	9769	1			T1	14		T2	33		T5	4
valid_sources[0x1a]	9903	1			T1	5		T2	37		T4	4
valid_sources[0x1b]	6799	1			T1	3		T2	33		T5	1
valid_sources[0x1c]	7776	1			T1	8		T2	41		T5	1
valid_sources[0x1d]	7278	1			T1	13		T2	37		T5	1
valid_sources[0x1e]	9023	1			T1	16		T2	37		T7	21
valid_sources[0x1f]	7266	1			T2	29		T5	2		T7	38
valid_sources[0x20]	6752	1			T1	9		T2	41		T7	47
valid_sources[0x21]	9416	1			T1	4		T2	25		T5	4
valid_sources[0x22]	16770	1			T1	6		T2	25		T5	2
valid_sources[0x23]	11374	1			T1	4		T2	34		T5	6
valid_sources[0x24]	11420	1			T1	13		T2	29		T4	4
valid_sources[0x25]	7709	1			T2	26		T4	3		T5	3
valid_sources[0x26]	7782	1			T1	6		T2	41		T7	46
valid_sources[0x27]	7006	1			T1	20		T2	40		T5	4
valid_sources[0x28]	11335	1			T1	1		T2	34		T5	5
valid_sources[0x29]	8725	1			T1	9		T2	41		T5	5
valid_sources[0x2a]	7111	1			T1	10		T2	22		T5	2
valid_sources[0x2b]	6804	1			T1	17		T2	33		T5	1
valid_sources[0x2c]	7724	1			T2	27		T5	1		T7	21
valid_sources[0x2d]	10722	1			T1	3		T2	26		T5	2
valid_sources[0x2e]	11203	1			T1	19		T2	25		T5	3
valid_sources[0x2f]	6969	1			T1	1		T2	31		T5	1
valid_sources[0x30]	8200	1			T1	3		T2	28		T5	1
valid_sources[0x31]	9581	1			T1	11		T2	38		T5	2
valid_sources[0x32]	7215	1			T1	9		T2	40		T5	2
valid_sources[0x33]	7735	1			T1	4		T2	49		T5	5
valid_sources[0x34]	6685	1			T1	12		T2	22		T5	1
valid_sources[0x35]	7243	1			T1	20		T2	43		T5	2
valid_sources[0x36]	6543	1			T1	22		T2	31		T5	3
valid_sources[0x37]	12475	1			T1	11		T2	32		T5	4
valid_sources[0x38]	6899	1			T1	9		T2	34		T5	4
valid_sources[0x39]	7007	1			T1	5		T2	26		T3	16
valid_sources[0x3a]	8065	1			T1	9		T2	27		T5	8
valid_sources[0x3b]	6905	1			T1	11		T2	26		T4	2
valid_sources[0x3c]	7202	1			T1	12		T2	31		T5	7
valid_sources[0x3d]	6635	1			T1	14		T2	39		T5	1
valid_sources[0x3e]	12042	1			T1	10		T2	37		T5	7
valid_sources[0x3f]	11186	1			T1	16		T2	38		T5	5
valid_sources[0x40]	11303	1			T1	10		T2	36		T5	1
valid_sources[0x41]	6878	1			T1	20		T2	30		T4	1
valid_sources[0x42]	6841	1			T1	10		T2	17		T5	3
valid_sources[0x43]	7171	1			T1	7		T2	37		T5	1
valid_sources[0x44]	8016	1			T1	9		T2	41		T4	8
valid_sources[0x45]	7720	1			T1	3		T2	29		T4	1
valid_sources[0x46]	9541	1			T1	3		T2	21		T5	1
valid_sources[0x47]	7230	1			T1	6		T2	28		T5	5
valid_sources[0x48]	6942	1			T1	27		T2	40		T5	1
valid_sources[0x49]	9857	1			T1	1		T2	28		T5	3
valid_sources[0x4a]	6970	1			T1	5		T2	31		T5	1
valid_sources[0x4b]	11564	1			T1	8		T2	22		T5	3
valid_sources[0x4c]	6814	1			T2	37		T4	3		T5	4
valid_sources[0x4d]	8264	1			T1	8		T2	40		T4	2
valid_sources[0x4e]	6965	1			T1	2		T2	40		T5	5
valid_sources[0x4f]	19994	1			T1	12		T2	37		T4	2
valid_sources[0x50]	6885	1			T1	7		T2	36		T5	6
valid_sources[0x51]	20735	1			T1	8		T2	36		T4	1
valid_sources[0x52]	9188	1			T1	8		T2	31		T4	1
valid_sources[0x53]	10972	1			T1	7		T2	34		T5	8
valid_sources[0x54]	7011	1			T1	1		T2	36		T5	5
valid_sources[0x55]	7270	1			T1	22		T2	37		T5	1
valid_sources[0x56]	7879	1			T1	5		T2	29		T5	1
valid_sources[0x57]	6999	1			T1	2		T2	22		T5	2
valid_sources[0x58]	7145	1			T1	3		T2	25		T4	2
valid_sources[0x59]	6787	1			T1	17		T2	31		T5	4
valid_sources[0x5a]	8170	1			T1	13		T2	33		T5	2
valid_sources[0x5b]	7697	1			T1	1		T2	35		T5	9
valid_sources[0x5c]	8567	1			T1	3		T2	39		T5	1
valid_sources[0x5d]	7048	1			T1	7		T2	25		T5	6
valid_sources[0x5e]	13528	1			T1	4		T2	23		T7	39
valid_sources[0x5f]	9790	1			T1	2		T2	25		T4	2
valid_sources[0x60]	6738	1			T1	8		T2	40		T5	1
valid_sources[0x61]	8827	1			T1	15		T2	32		T5	3
valid_sources[0x62]	12395	1			T1	11		T2	28		T3	8
valid_sources[0x63]	13311	1			T1	7		T2	50		T5	1
valid_sources[0x64]	9472	1			T1	19		T2	44		T5	2
valid_sources[0x65]	8151	1			T1	2		T2	32		T5	4
valid_sources[0x66]	6941	1			T1	17		T2	45		T5	2
valid_sources[0x67]	6842	1			T1	6		T2	38		T5	2
valid_sources[0x68]	8052	1			T1	4		T2	41		T5	1
valid_sources[0x69]	11182	1			T1	9		T2	30		T5	7
valid_sources[0x6a]	11353	1			T1	8		T2	37		T5	5
valid_sources[0x6b]	11430	1			T1	8		T2	41		T3	5
valid_sources[0x6c]	11673	1			T1	6		T2	49		T5	6
valid_sources[0x6d]	6997	1			T1	4		T2	35		T5	6
valid_sources[0x6e]	7578	1			T1	4		T2	42		T5	3
valid_sources[0x6f]	12137	1			T1	2		T2	47		T5	3
valid_sources[0x70]	8138	1			T1	2		T2	41		T5	7
valid_sources[0x71]	9297	1			T1	9		T2	22		T4	3
valid_sources[0x72]	7072	1			T1	3		T2	37		T5	1
valid_sources[0x73]	7022	1			T1	17		T2	32		T4	1
valid_sources[0x74]	11125	1			T1	3		T2	33		T4	1
valid_sources[0x75]	6802	1			T1	8		T2	21		T5	1
valid_sources[0x76]	12321	1			T1	14		T2	30		T3	1
valid_sources[0x77]	11745	1			T1	12		T2	31		T5	4
valid_sources[0x78]	8102	1			T1	9		T2	41		T5	1
valid_sources[0x79]	10370	1			T1	3		T2	25		T5	6
valid_sources[0x7a]	6710	1			T1	8		T2	29		T4	5
valid_sources[0x7b]	7132	1			T1	6		T2	21		T5	2
valid_sources[0x7c]	6865	1			T1	9		T2	34		T7	36
valid_sources[0x7d]	7183	1			T1	16		T2	21		T5	2
valid_sources[0x7e]	10760	1			T1	8		T2	33		T7	35
valid_sources[0x7f]	7015	1			T1	15		T2	34		T5	3
valid_sources[0x80]	6588	1			T1	5		T2	39		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

984039

1

T1

958

T2

6112

T4

40

values[0x0]

all_enables

biggest_size

77465

1

T1

55

T2

162

T3

13

values[0x1]

all_enables

biggest_size

55839

1

T1

46

T2

105

T3

6