Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29012	1			T1	6		T2	18		T5	194
auto[PWRUP]	117	1			T5	2		T10	1		T198	1
auto[ONEST_0]	69	1			T7	1		T10	1		T43	2
auto[ONEST_021]	21	1			T43	1		T41	1		T143	2
auto[ONEST_1]	97	1			T7	2		T10	3		T15	2
auto[ONEST_DONE]	4	1			T206	1		T207	1		T147	1
auto[LP_0]	117	1			T7	1		T43	2		T154	1
auto[LP_021]	29	1			T47	1		T208	2		T143	1
auto[LP_1]	120	1			T5	2		T7	2		T43	2
auto[LP_EVAL]	84	1			T10	2		T15	3		T43	1
auto[LP_SLP]	473	1			T5	4		T7	6		T10	6
auto[LP_PWRUP]	28	1			T43	1		T154	1		T208	1
auto[NP_0]	147	1			T5	2		T7	1		T15	1
auto[NP_021]	40	1			T10	1		T43	1		T47	1
auto[NP_1]	173	1			T5	1		T7	4		T10	3
auto[NP_EVAL]	30	1			T5	1		T10	1		T15	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T5

1

T209

1

T210

1

min

28487

1

T1

6

T2

18

T5

183

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28491	1			T1	6		T2	18		T5	183
pow[0x1]	3	1			T143	1		T211	1		T212	1
pow[0x2]	18	1			T5	1		T10	1		T43	1
pow[0x3]	34	1			T7	1		T15	1		T47	1
pow[0x4]	63	1			T5	1		T7	1		T10	2
pow[0x5]	134	1			T7	1		T10	1		T15	2
pow[0x6]	257	1			T5	1		T7	2		T10	1
pow[0x7]	560	1			T5	5		T7	9		T10	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

202

1

T5

1

T7

5

T10

1

min

28066

1

T1

6

T2

18

T5

179

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28067	1			T1	6		T2	18		T5	179
pow[0x2]	1	1			T154	1		-	-		-	-
pow[0x5]	1	1			T213	1		-	-		-	-
pow[0x6]	3	1			T46	1		T20	1		T214	1
pow[0x7]	2	1			T215	1		T216	1		-	-
pow[0x8]	4	1			T43	1		T217	1		T218	1
pow[0x9]	11	1			T154	1		T219	1		T147	1
pow[0xa]	22	1			T7	1		T43	2		T198	1
pow[0xb]	39	1			T15	1		T43	1		T154	1
pow[0xc]	60	1			T5	1		T7	1		T198	2
pow[0xd]	147	1			T5	2		T7	3		T10	2
pow[0xe]	249	1			T5	3		T7	5		T15	1
pow[0xf]	583	1			T5	10		T7	3		T10	5