Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2246	1			T1	3		T5	16		T6	6
auto[PWRUP]	106	1			T5	2		T7	4		T43	2
auto[ONEST_0]	80	1			T5	1		T7	1		T15	1
auto[ONEST_021]	15	1			T15	1		T82	1		T20	1
auto[ONEST_1]	76	1			T6	1		T7	1		T14	1
auto[ONEST_DONE]	5	1			T7	1		T43	1		T265	1
auto[LP_0]	118	1			T5	1		T6	1		T7	1
auto[LP_021]	39	1			T5	1		T7	1		T10	2
auto[LP_1]	137	1			T5	1		T7	1		T15	3
auto[LP_EVAL]	63	1			T7	1		T10	2		T43	1
auto[LP_SLP]	510	1			T5	5		T7	6		T10	10
auto[LP_PWRUP]	26	1			T10	1		T43	1		T154	2
auto[NP_0]	228	1			T5	3		T6	2		T7	3
auto[NP_021]	50	1			T5	1		T7	1		T38	1
auto[NP_1]	194	1			T7	1		T10	3		T14	1
auto[NP_EVAL]	43	1			T10	1		T154	1		T37	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T219

1

T360

1

T361

1

min

1963

1

T1

3

T5

8

T6

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1978	1			T1	3		T5	8		T6	7
pow[0x1]	7	1			T198	1		T143	1		T206	1
pow[0x2]	12	1			T198	1		T143	1		T362	2
pow[0x3]	25	1			T5	1		T43	1		T154	2
pow[0x4]	74	1			T6	1		T7	1		T15	1
pow[0x5]	116	1			T5	1		T7	3		T10	3
pow[0x6]	263	1			T5	4		T7	7		T10	2
pow[0x7]	497	1			T5	4		T6	1		T7	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

176

1

T5

3

T7

2

T10

2

min

1352

1

T1

3

T5

4

T6

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1358	1			T1	3		T5	4		T6	6
pow[0x1]	9	1			T14	2		T15	1		T318	2
pow[0x2]	34	1			T15	1		T43	1		T37	2
pow[0x3]	33	1			T16	2		T40	1		T18	2
pow[0x4]	71	1			T6	1		T38	4		T39	7
pow[0x6]	3	1			T210	1		T363	1		T364	1
pow[0x7]	1	1			T316	1		-	-		-	-
pow[0x8]	10	1			T43	1		T365	1		T44	1
pow[0x9]	5	1			T198	1		T206	1		T343	1
pow[0xa]	20	1			T7	1		T10	3		T154	1
pow[0xb]	28	1			T7	1		T10	1		T154	1
pow[0xc]	64	1			T5	2		T7	1		T43	2
pow[0xd]	167	1			T5	2		T7	4		T10	2
pow[0xe]	298	1			T5	3		T7	3		T10	2
pow[0xf]	563	1			T5	5		T6	1		T7	7