Line Coverage for Module :
adc_ctrl
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
49 |
1 |
1 |
Cond Coverage for Module :
adc_ctrl
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 49
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T64,T65,T66 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T64,T66,T76 |
Toggle Coverage for Module :
adc_ctrl
| Total | Covered | Percent |
Totals |
34 |
34 |
100.00 |
Total Bits |
368 |
368 |
100.00 |
Total Bits 0->1 |
184 |
184 |
100.00 |
Total Bits 1->0 |
184 |
184 |
100.00 |
| | | |
Ports |
34 |
34 |
100.00 |
Port Bits |
368 |
368 |
100.00 |
Port Bits 0->1 |
184 |
184 |
100.00 |
Port Bits 1->0 |
184 |
184 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
clk_aon_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T5,T6 |
Yes |
T1,T2,T3 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T1,T5,T6 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T1,T4,T5 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T2,T5,T6 |
Yes |
T2,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T6,T14,T15 |
Yes |
T6,T14,T15 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T4 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T4 |
Yes |
T1,T2,T4 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T64,T66,T76 |
Yes |
T64,T66,T76 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T64,T66,T76 |
Yes |
T64,T66,T76 |
OUTPUT |
adc_o.pd |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
adc_o.channel_sel[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
adc_i.data_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
adc_i.data[9:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
intr_match_pending_o |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
OUTPUT |
wkup_req_o |
Yes |
Yes |
T1,T5,T6 |
Yes |
T1,T5,T6 |
OUTPUT |
*Tests covering at least one bit in the range
Assert Coverage for Module :
adc_ctrl
Assertion Details
AdcKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
782973 |
782938 |
0 |
0 |
T2 |
471770 |
471769 |
0 |
0 |
T3 |
338898 |
338807 |
0 |
0 |
T4 |
564023 |
563965 |
0 |
0 |
T5 |
134416 |
134392 |
0 |
0 |
T6 |
813482 |
798532 |
0 |
0 |
T7 |
199706 |
199672 |
0 |
0 |
T8 |
132169 |
132094 |
0 |
0 |
T9 |
195509 |
195501 |
0 |
0 |
T10 |
104560 |
104527 |
0 |
0 |
AlertsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
782973 |
782938 |
0 |
0 |
T2 |
471770 |
471769 |
0 |
0 |
T3 |
338898 |
338807 |
0 |
0 |
T4 |
564023 |
563965 |
0 |
0 |
T5 |
134416 |
134392 |
0 |
0 |
T6 |
813482 |
798532 |
0 |
0 |
T7 |
199706 |
199672 |
0 |
0 |
T8 |
132169 |
132094 |
0 |
0 |
T9 |
195509 |
195501 |
0 |
0 |
T10 |
104560 |
104527 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
90 |
0 |
0 |
T19 |
919830 |
0 |
0 |
0 |
T57 |
717062 |
20 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T59 |
0 |
20 |
0 |
0 |
T77 |
0 |
20 |
0 |
0 |
T78 |
0 |
10 |
0 |
0 |
T79 |
481822 |
0 |
0 |
0 |
T80 |
118724 |
0 |
0 |
0 |
T81 |
174112 |
0 |
0 |
0 |
T82 |
892716 |
0 |
0 |
0 |
T83 |
150397 |
0 |
0 |
0 |
T84 |
172421 |
0 |
0 |
0 |
T85 |
6212 |
0 |
0 |
0 |
T86 |
104809 |
0 |
0 |
0 |
IntrKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
782973 |
782938 |
0 |
0 |
T2 |
471770 |
471769 |
0 |
0 |
T3 |
338898 |
338807 |
0 |
0 |
T4 |
564023 |
563965 |
0 |
0 |
T5 |
134416 |
134392 |
0 |
0 |
T6 |
813482 |
798532 |
0 |
0 |
T7 |
199706 |
199672 |
0 |
0 |
T8 |
132169 |
132094 |
0 |
0 |
T9 |
195509 |
195501 |
0 |
0 |
T10 |
104560 |
104527 |
0 |
0 |
TlOAReadyKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
782973 |
782938 |
0 |
0 |
T2 |
471770 |
471769 |
0 |
0 |
T3 |
338898 |
338807 |
0 |
0 |
T4 |
564023 |
563965 |
0 |
0 |
T5 |
134416 |
134392 |
0 |
0 |
T6 |
813482 |
798532 |
0 |
0 |
T7 |
199706 |
199672 |
0 |
0 |
T8 |
132169 |
132094 |
0 |
0 |
T9 |
195509 |
195501 |
0 |
0 |
T10 |
104560 |
104527 |
0 |
0 |
TlODValidKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
782973 |
782938 |
0 |
0 |
T2 |
471770 |
471769 |
0 |
0 |
T3 |
338898 |
338807 |
0 |
0 |
T4 |
564023 |
563965 |
0 |
0 |
T5 |
134416 |
134392 |
0 |
0 |
T6 |
813482 |
798532 |
0 |
0 |
T7 |
199706 |
199672 |
0 |
0 |
T8 |
132169 |
132094 |
0 |
0 |
T9 |
195509 |
195501 |
0 |
0 |
T10 |
104560 |
104527 |
0 |
0 |
WakeKnown
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
782973 |
782938 |
0 |
0 |
T2 |
471770 |
471769 |
0 |
0 |
T3 |
338898 |
338807 |
0 |
0 |
T4 |
564023 |
563965 |
0 |
0 |
T5 |
134416 |
134392 |
0 |
0 |
T6 |
813482 |
798532 |
0 |
0 |
T7 |
199706 |
199672 |
0 |
0 |
T8 |
132169 |
132094 |
0 |
0 |
T9 |
195509 |
195501 |
0 |
0 |
T10 |
104560 |
104527 |
0 |
0 |