Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1210276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1185553

1

T1

908

T2

964

T3

396

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2101636	1			T1	1676		T2	1668		T4	2513
values[0x0]	146831	1			T1	100		T2	132		T3	516
values[0x1]	147362	1			T1	108		T2	92		T3	486

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	969276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1426553

1

T1

1124

T2

1132

T3

466

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19888	1			T1	2		T3	1		T4	17
valid_sources[0x01]	11948	1			T1	6		T3	10		T4	4
valid_sources[0x02]	6815	1			T1	12		T3	3		T4	13
valid_sources[0x03]	16727	1			T1	5		T3	4		T4	20
valid_sources[0x04]	14139	1			T1	5		T4	19		T9	11
valid_sources[0x05]	11040	1			T1	7		T3	6		T4	11
valid_sources[0x06]	6826	1			T1	9		T3	6		T4	10
valid_sources[0x07]	8185	1			T1	5		T3	2		T4	10
valid_sources[0x08]	11227	1			T1	2		T3	9		T4	15
valid_sources[0x09]	6552	1			T1	9		T4	14		T9	11
valid_sources[0x0a]	12249	1			T1	9		T3	4		T4	5
valid_sources[0x0b]	8632	1			T1	7		T3	2		T4	8
valid_sources[0x0c]	9910	1			T1	7		T4	12		T9	15
valid_sources[0x0d]	7163	1			T1	8		T3	2		T4	7
valid_sources[0x0e]	6794	1			T1	5		T4	3		T9	13
valid_sources[0x0f]	6714	1			T1	11		T3	4		T4	14
valid_sources[0x10]	7308	1			T1	7		T3	9		T4	10
valid_sources[0x11]	8399	1			T1	9		T3	5		T4	5
valid_sources[0x12]	7298	1			T1	10		T4	20		T5	40
valid_sources[0x13]	9687	1			T1	16		T3	4		T4	5
valid_sources[0x14]	11569	1			T1	10		T4	4		T7	1
valid_sources[0x15]	6800	1			T1	13		T3	1		T4	7
valid_sources[0x16]	7066	1			T1	11		T4	13		T5	13
valid_sources[0x17]	6962	1			T1	6		T3	7		T4	6
valid_sources[0x18]	16775	1			T1	9		T3	10		T4	16
valid_sources[0x19]	14366	1			T1	7		T3	8		T4	9
valid_sources[0x1a]	9696	1			T1	10		T3	11		T4	25
valid_sources[0x1b]	15611	1			T1	11		T3	1		T4	15
valid_sources[0x1c]	6835	1			T1	10		T3	4		T4	20
valid_sources[0x1d]	8095	1			T1	5		T3	6		T4	4
valid_sources[0x1e]	10151	1			T1	9		T3	2		T4	16
valid_sources[0x1f]	7148	1			T1	14		T3	5		T4	15
valid_sources[0x20]	6018	1			T1	6		T3	1		T4	4
valid_sources[0x21]	21610	1			T1	7		T3	15		T4	10
valid_sources[0x22]	11708	1			T1	5		T3	3		T4	12
valid_sources[0x23]	8278	1			T1	5		T3	3		T4	13
valid_sources[0x24]	7311	1			T1	9		T4	15		T8	10
valid_sources[0x25]	8646	1			T1	5		T3	3		T4	10
valid_sources[0x26]	6864	1			T1	6		T4	12		T8	3
valid_sources[0x27]	9854	1			T1	10		T4	10		T9	19
valid_sources[0x28]	6777	1			T1	5		T3	2		T4	10
valid_sources[0x29]	8546	1			T1	5		T3	2		T4	6
valid_sources[0x2a]	16578	1			T1	8		T4	8		T7	2
valid_sources[0x2b]	15927	1			T1	8		T3	6		T4	5
valid_sources[0x2c]	6826	1			T1	5		T3	3		T4	8
valid_sources[0x2d]	6880	1			T1	8		T3	4		T4	9
valid_sources[0x2e]	8264	1			T1	7		T3	8		T4	7
valid_sources[0x2f]	8872	1			T1	8		T4	9		T9	15
valid_sources[0x30]	6817	1			T1	10		T3	4		T4	10
valid_sources[0x31]	10577	1			T1	7		T3	6		T4	10
valid_sources[0x32]	11313	1			T1	5		T4	13		T5	27
valid_sources[0x33]	6648	1			T1	10		T3	4		T4	16
valid_sources[0x34]	6885	1			T1	5		T3	3		T4	18
valid_sources[0x35]	7701	1			T1	2		T3	4		T4	4
valid_sources[0x36]	6956	1			T1	7		T4	13		T7	1
valid_sources[0x37]	11157	1			T1	8		T3	4		T4	11
valid_sources[0x38]	6614	1			T1	9		T3	1		T4	4
valid_sources[0x39]	7195	1			T1	1		T3	2		T4	8
valid_sources[0x3a]	6930	1			T1	5		T4	4		T8	5
valid_sources[0x3b]	7642	1			T1	7		T4	14		T9	22
valid_sources[0x3c]	7563	1			T1	2		T3	2		T4	13
valid_sources[0x3d]	9114	1			T1	5		T3	4		T4	10
valid_sources[0x3e]	7018	1			T1	5		T3	9		T4	6
valid_sources[0x3f]	6500	1			T1	7		T3	9		T4	5
valid_sources[0x40]	8912	1			T1	8		T3	2		T4	20
valid_sources[0x41]	7227	1			T1	7		T3	1		T4	7
valid_sources[0x42]	7021	1			T1	4		T3	9		T4	15
valid_sources[0x43]	7821	1			T1	12		T4	9		T5	14
valid_sources[0x44]	7881	1			T1	8		T3	7		T4	7
valid_sources[0x45]	9726	1			T1	12		T4	9		T9	15
valid_sources[0x46]	11055	1			T1	7		T3	6		T4	6
valid_sources[0x47]	12869	1			T1	8		T3	4		T4	7
valid_sources[0x48]	10609	1			T1	2		T3	1		T4	21
valid_sources[0x49]	7341	1			T1	7		T4	4		T7	1
valid_sources[0x4a]	6845	1			T1	7		T3	4		T4	8
valid_sources[0x4b]	7884	1			T1	5		T3	5		T4	18
valid_sources[0x4c]	7591	1			T1	8		T3	7		T4	28
valid_sources[0x4d]	8162	1			T1	4		T3	3		T4	9
valid_sources[0x4e]	9876	1			T1	11		T3	3		T4	8
valid_sources[0x4f]	9480	1			T1	12		T4	13		T7	1
valid_sources[0x50]	15852	1			T1	10		T3	2		T4	9
valid_sources[0x51]	9848	1			T1	7		T3	11		T4	15
valid_sources[0x52]	8935	1			T1	6		T3	2		T4	5
valid_sources[0x53]	9307	1			T1	10		T4	5		T8	1
valid_sources[0x54]	9327	1			T1	4		T3	2		T4	5
valid_sources[0x55]	9180	1			T1	7		T4	13		T8	1
valid_sources[0x56]	9685	1			T1	5		T3	6		T4	5
valid_sources[0x57]	15915	1			T1	7		T3	6		T4	20
valid_sources[0x58]	8458	1			T1	8		T3	2		T4	7
valid_sources[0x59]	11782	1			T1	4		T3	3		T4	25
valid_sources[0x5a]	6897	1			T1	8		T3	2		T4	16
valid_sources[0x5b]	11618	1			T1	4		T3	3		T4	11
valid_sources[0x5c]	9603	1			T1	8		T3	1		T4	9
valid_sources[0x5d]	10333	1			T1	11		T3	4		T4	5
valid_sources[0x5e]	9026	1			T1	7		T3	8		T4	3
valid_sources[0x5f]	6679	1			T1	5		T3	11		T4	3
valid_sources[0x60]	7022	1			T1	18		T3	5		T4	12
valid_sources[0x61]	6961	1			T1	6		T3	4		T4	6
valid_sources[0x62]	7249	1			T1	6		T3	3		T4	10
valid_sources[0x63]	7091	1			T1	7		T4	8		T9	19
valid_sources[0x64]	7205	1			T1	14		T3	6		T4	10
valid_sources[0x65]	6885	1			T1	8		T3	4		T4	11
valid_sources[0x66]	7551	1			T1	8		T3	1		T4	6
valid_sources[0x67]	7004	1			T1	6		T3	2		T4	10
valid_sources[0x68]	7750	1			T1	5		T3	6		T4	12
valid_sources[0x69]	6663	1			T1	7		T3	2		T4	10
valid_sources[0x6a]	6791	1			T1	7		T3	6		T4	10
valid_sources[0x6b]	7318	1			T1	3		T3	18		T4	11
valid_sources[0x6c]	7021	1			T1	12		T3	12		T4	21
valid_sources[0x6d]	6767	1			T1	9		T3	4		T4	17
valid_sources[0x6e]	12074	1			T1	4		T3	5		T4	8
valid_sources[0x6f]	6686	1			T1	6		T3	1		T4	12
valid_sources[0x70]	11160	1			T1	11		T4	20		T9	26
valid_sources[0x71]	7208	1			T1	12		T3	5		T4	8
valid_sources[0x72]	7526	1			T1	8		T3	1		T4	27
valid_sources[0x73]	6696	1			T1	5		T3	4		T4	6
valid_sources[0x74]	17342	1			T1	8		T4	18		T5	59
valid_sources[0x75]	11968	1			T1	11		T3	7		T4	8
valid_sources[0x76]	7925	1			T1	7		T3	1		T4	12
valid_sources[0x77]	14219	1			T1	10		T3	4		T4	8
valid_sources[0x78]	19724	1			T1	5		T3	11		T4	12
valid_sources[0x79]	7796	1			T1	3		T3	2		T4	15
valid_sources[0x7a]	7386	1			T1	11		T3	2		T4	2
valid_sources[0x7b]	8955	1			T1	8		T3	1		T4	7
valid_sources[0x7c]	7758	1			T1	4		T3	2		T4	18
valid_sources[0x7d]	11371	1			T1	5		T3	8		T4	10
valid_sources[0x7e]	8104	1			T1	5		T3	2		T4	4
valid_sources[0x7f]	12064	1			T1	10		T3	8		T4	13
valid_sources[0x80]	8986	1			T1	12		T2	1892		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1046584

1

T1

805

T2

859

T4

1190

values[0x0]

all_enables

biggest_size

80759

1

T1

60

T2

68

T3

242

values[0x1]

all_enables

biggest_size

58210

1

T1

43

T2

37

T3

154