Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29531	1			T1	18		T2	15		T3	229
auto[PWRUP]	94	1			T3	3		T51	3		T52	1
auto[ONEST_0]	64	1			T3	1		T36	1		T51	1
auto[ONEST_021]	21	1			T56	1		T55	2		T57	1
auto[ONEST_1]	76	1			T36	1		T51	2		T52	2
auto[ONEST_DONE]	3	1			T176	1		T177	1		T178	1
auto[LP_0]	118	1			T3	3		T36	1		T51	1
auto[LP_021]	22	1			T3	1		T32	1		T54	1
auto[LP_1]	126	1			T3	1		T36	1		T52	2
auto[LP_EVAL]	72	1			T3	2		T36	2		T51	1
auto[LP_SLP]	449	1			T3	6		T36	1		T51	12
auto[LP_PWRUP]	23	1			T52	1		T32	1		T179	1
auto[NP_0]	148	1			T3	5		T36	2		T51	3
auto[NP_021]	25	1			T36	1		T51	1		T32	1
auto[NP_1]	159	1			T3	4		T36	4		T51	1
auto[NP_EVAL]	20	1			T32	1		T180	1		T181	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T51

1

T54

1

T182

1

min

28987

1

T1

18

T2

15

T3

229

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28998	1			T1	18		T2	15		T3	229
pow[0x1]	4	1			T55	1		T183	1		T184	1
pow[0x2]	10	1			T51	1		T56	1		T183	1
pow[0x3]	24	1			T54	2		T185	2		T180	1
pow[0x4]	65	1			T3	1		T32	3		T179	2
pow[0x5]	119	1			T3	2		T51	3		T52	2
pow[0x6]	250	1			T3	2		T36	2		T51	3
pow[0x7]	476	1			T3	5		T36	4		T51	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

165

1

T3

1

T36

3

T51

3

min

28567

1

T1

18

T2

15

T3

224

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28567	1			T1	18		T2	15		T3	224
pow[0x4]	1	1			T186	1		-	-		-	-
pow[0x6]	1	1			T187	1		-	-		-	-
pow[0x7]	2	1			T188	1		T189	1		-	-
pow[0x8]	5	1			T182	1		T190	1		T22	1
pow[0x9]	10	1			T52	1		T54	1		T183	2
pow[0xa]	20	1			T32	1		T56	1		T191	1
pow[0xb]	36	1			T52	1		T32	1		T54	2
pow[0xc]	73	1			T51	2		T52	1		T32	1
pow[0xd]	129	1			T3	2		T51	3		T52	1
pow[0xe]	294	1			T3	6		T36	3		T51	1
pow[0xf]	540	1			T3	7		T36	5		T51	12