Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	100.00	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	0	45	100.00

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2264	1			T3	18		T5	3		T36	8
auto[PWRUP]	126	1			T3	1		T36	4		T51	5
auto[ONEST_0]	72	1			T3	1		T51	1		T52	1
auto[ONEST_021]	21	1			T55	1		T57	1		T140	1
auto[ONEST_1]	82	1			T52	2		T14	1		T32	1
auto[ONEST_DONE]	2	1			T201	1		T189	1		-	-
auto[LP_0]	111	1			T3	2		T36	2		T51	2
auto[LP_021]	21	1			T52	1		T54	1		T319	1
auto[LP_1]	124	1			T3	1		T36	1		T52	1
auto[LP_EVAL]	50	1			T3	1		T36	1		T51	1
auto[LP_SLP]	521	1			T3	11		T36	1		T51	8
auto[LP_PWRUP]	27	1			T52	1		T54	2		T185	1
auto[NP_0]	230	1			T3	2		T36	2		T51	2
auto[NP_021]	50	1			T51	2		T32	1		T37	1
auto[NP_1]	244	1			T3	4		T51	1		T34	2
auto[NP_EVAL]	35	1			T14	1		T181	1		T18	1
auto[NP_DONE]	1	1			T320	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T179

1

T55

1

T183

1

min

2041

1

T3

11

T5

3

T36

3

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2056	1			T3	11		T5	3		T36	3
pow[0x1]	9	1			T25	1		T191	1		T194	1
pow[0x2]	25	1			T52	1		T54	1		T179	1
pow[0x3]	35	1			T36	1		T32	1		T180	1
pow[0x4]	56	1			T51	1		T52	1		T32	1
pow[0x5]	110	1			T3	4		T51	3		T52	2
pow[0x6]	250	1			T3	4		T36	2		T51	6
pow[0x7]	453	1			T3	8		T36	4		T51	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

189

1

T3

3

T51

1

T52

3

min

1455

1

T3

2

T5

3

T49

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1466	1			T3	2		T5	3		T49	3
pow[0x1]	11	1			T15	1		T37	2		T279	1
pow[0x2]	39	1			T35	1		T15	1		T230	6
pow[0x3]	39	1			T35	1		T14	1		T25	3
pow[0x4]	74	1			T34	2		T35	2		T14	4
pow[0x5]	2	1			T288	1		T321	1		-	-
pow[0x6]	4	1			T56	1		T322	1		T321	1
pow[0x7]	6	1			T320	1		T323	1		T274	1
pow[0x8]	3	1			T201	1		T324	1		T325	1
pow[0x9]	8	1			T36	1		T51	1		T319	1
pow[0xa]	17	1			T52	1		T180	1		T191	1
pow[0xb]	24	1			T51	2		T54	1		T180	1
pow[0xc]	57	1			T36	1		T51	2		T37	1
pow[0xd]	118	1			T3	2		T36	1		T51	1
pow[0xe]	283	1			T3	8		T36	4		T51	6
pow[0xf]	544	1			T3	15		T36	6		T51	13