Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1200380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1171999

1

T1

26

T2

382

T3

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2069414	1			T3	81		T4	81		T5	842
values[0x0]	151226	1			T1	21		T2	461		T3	32
values[0x1]	151739	1			T1	19		T2	488		T3	31

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	961582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1410797

1

T1

28

T2

478

T3

78

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7222	1			T2	1		T5	1		T6	29
valid_sources[0x01]	7254	1			T2	4		T5	3		T6	26
valid_sources[0x02]	9780	1			T2	6		T5	3		T6	36
valid_sources[0x03]	7882	1			T2	3		T4	5		T5	2
valid_sources[0x04]	20352	1			T2	5		T4	1		T5	7
valid_sources[0x05]	7167	1			T2	5		T5	2		T6	24
valid_sources[0x06]	6959	1			T2	1		T5	7		T6	37
valid_sources[0x07]	11770	1			T2	4		T5	5		T6	22
valid_sources[0x08]	7818	1			T2	1		T4	1		T5	7
valid_sources[0x09]	11497	1			T5	3		T6	43		T7	17
valid_sources[0x0a]	6867	1			T2	3		T5	4		T6	25
valid_sources[0x0b]	12295	1			T2	2		T4	1		T5	3
valid_sources[0x0c]	7098	1			T2	4		T5	4		T6	41
valid_sources[0x0d]	7072	1			T2	2		T5	7		T6	30
valid_sources[0x0e]	21953	1			T2	6		T4	1		T5	3
valid_sources[0x0f]	12388	1			T2	2		T5	4		T6	30
valid_sources[0x10]	20406	1			T2	6		T5	2		T6	55
valid_sources[0x11]	7328	1			T2	5		T5	3		T6	50
valid_sources[0x12]	7806	1			T2	10		T5	5		T6	22
valid_sources[0x13]	7696	1			T2	1		T5	4		T6	13
valid_sources[0x14]	11121	1			T2	1		T4	3		T5	11
valid_sources[0x15]	11379	1			T2	7		T5	4		T6	28
valid_sources[0x16]	11375	1			T2	8		T4	1		T5	12
valid_sources[0x17]	7685	1			T2	2		T5	2		T6	31
valid_sources[0x18]	6794	1			T2	5		T4	1		T5	2
valid_sources[0x19]	7820	1			T1	1		T2	1		T5	6
valid_sources[0x1a]	19961	1			T2	6		T5	7		T6	36
valid_sources[0x1b]	7728	1			T2	3		T5	2		T6	28
valid_sources[0x1c]	10064	1			T2	2		T5	5		T6	32
valid_sources[0x1d]	8009	1			T2	4		T5	1		T6	49
valid_sources[0x1e]	10238	1			T2	3		T4	2		T5	4
valid_sources[0x1f]	7883	1			T2	1		T5	9		T6	51
valid_sources[0x20]	6989	1			T2	3		T4	1		T5	5
valid_sources[0x21]	7790	1			T2	3		T5	3		T6	33
valid_sources[0x22]	6998	1			T2	6		T5	7		T6	37
valid_sources[0x23]	7078	1			T2	1		T4	2		T5	2
valid_sources[0x24]	7913	1			T2	8		T4	1		T5	3
valid_sources[0x25]	7246	1			T2	6		T5	3		T6	50
valid_sources[0x26]	6981	1			T1	3		T2	3		T4	3
valid_sources[0x27]	6782	1			T2	1		T5	2		T6	29
valid_sources[0x28]	9661	1			T2	2		T6	10		T7	2
valid_sources[0x29]	12205	1			T2	4		T5	3		T6	28
valid_sources[0x2a]	6901	1			T2	8		T5	1		T6	26
valid_sources[0x2b]	7121	1			T2	7		T5	7		T6	47
valid_sources[0x2c]	7648	1			T2	3		T5	4		T6	39
valid_sources[0x2d]	11439	1			T2	1		T5	5		T6	30
valid_sources[0x2e]	7118	1			T2	3		T5	3		T6	35
valid_sources[0x2f]	11150	1			T5	3		T6	45		T7	11
valid_sources[0x30]	12671	1			T2	2		T5	10		T6	20
valid_sources[0x31]	11613	1			T2	5		T5	5		T6	31
valid_sources[0x32]	8188	1			T2	6		T5	5		T6	26
valid_sources[0x33]	16685	1			T2	7		T4	1		T5	6
valid_sources[0x34]	7835	1			T2	4		T5	1		T6	22
valid_sources[0x35]	18274	1			T2	6		T5	5		T6	41
valid_sources[0x36]	12228	1			T4	1		T5	3		T6	36
valid_sources[0x37]	7432	1			T2	2		T5	2		T6	45
valid_sources[0x38]	12659	1			T2	3		T5	5		T6	33
valid_sources[0x39]	6898	1			T2	5		T6	31		T7	28
valid_sources[0x3a]	7039	1			T2	5		T5	7		T6	28
valid_sources[0x3b]	11962	1			T2	2		T4	2		T6	28
valid_sources[0x3c]	8650	1			T2	2		T5	7		T6	46
valid_sources[0x3d]	7730	1			T2	7		T5	6		T6	31
valid_sources[0x3e]	20743	1			T2	7		T6	37		T7	7
valid_sources[0x3f]	8258	1			T1	6		T2	6		T4	4
valid_sources[0x40]	7699	1			T2	4		T3	144		T5	6
valid_sources[0x41]	9931	1			T2	6		T4	1		T5	5
valid_sources[0x42]	14415	1			T2	4		T4	1		T5	2
valid_sources[0x43]	7059	1			T2	2		T5	7		T6	41
valid_sources[0x44]	8096	1			T2	1		T4	1		T5	9
valid_sources[0x45]	16563	1			T2	5		T4	1		T5	3
valid_sources[0x46]	11794	1			T2	7		T4	2		T5	1
valid_sources[0x47]	6877	1			T2	3		T4	2		T5	1
valid_sources[0x48]	11098	1			T2	2		T4	1		T5	4
valid_sources[0x49]	9889	1			T2	4		T5	7		T6	44
valid_sources[0x4a]	7357	1			T2	2		T5	4		T6	33
valid_sources[0x4b]	10621	1			T2	3		T4	2		T6	30
valid_sources[0x4c]	7308	1			T5	6		T6	20		T7	7
valid_sources[0x4d]	12172	1			T2	7		T5	6		T6	58
valid_sources[0x4e]	7106	1			T2	1		T4	1		T5	2
valid_sources[0x4f]	6924	1			T2	5		T5	6		T6	35
valid_sources[0x50]	7354	1			T2	3		T4	1		T5	2
valid_sources[0x51]	7442	1			T1	4		T2	1		T4	1
valid_sources[0x52]	7333	1			T2	9		T4	3		T5	7
valid_sources[0x53]	7575	1			T2	4		T5	2		T6	35
valid_sources[0x54]	8831	1			T2	4		T5	3		T6	24
valid_sources[0x55]	6848	1			T2	5		T5	7		T6	21
valid_sources[0x56]	7443	1			T2	3		T5	1		T6	46
valid_sources[0x57]	8994	1			T2	2		T5	5		T6	28
valid_sources[0x58]	7479	1			T2	4		T4	3		T5	1
valid_sources[0x59]	11537	1			T2	5		T6	18		T7	24
valid_sources[0x5a]	7059	1			T2	1		T4	1		T5	5
valid_sources[0x5b]	10089	1			T2	5		T5	7		T6	35
valid_sources[0x5c]	11494	1			T2	5		T4	2		T5	5
valid_sources[0x5d]	11269	1			T2	2		T4	1		T5	4
valid_sources[0x5e]	13131	1			T2	3		T5	3		T6	31
valid_sources[0x5f]	7373	1			T2	3		T4	2		T5	10
valid_sources[0x60]	11931	1			T2	7		T5	1		T6	32
valid_sources[0x61]	9963	1			T1	4		T2	1		T5	3
valid_sources[0x62]	8160	1			T2	5		T4	2		T5	3
valid_sources[0x63]	7080	1			T2	5		T5	6		T6	43
valid_sources[0x64]	6951	1			T4	1		T5	7		T6	33
valid_sources[0x65]	11408	1			T2	4		T5	1		T6	46
valid_sources[0x66]	6879	1			T2	4		T6	13		T7	12
valid_sources[0x67]	7410	1			T2	1		T5	5		T6	42
valid_sources[0x68]	7391	1			T2	7		T5	1		T6	36
valid_sources[0x69]	11575	1			T1	1		T2	3		T5	1
valid_sources[0x6a]	9222	1			T2	5		T4	1		T6	26
valid_sources[0x6b]	7242	1			T2	3		T4	1		T6	44
valid_sources[0x6c]	7006	1			T2	7		T5	3		T6	32
valid_sources[0x6d]	7090	1			T2	8		T4	1		T5	4
valid_sources[0x6e]	15591	1			T2	7		T4	2		T6	49
valid_sources[0x6f]	6951	1			T2	7		T5	2		T6	37
valid_sources[0x70]	7520	1			T2	6		T4	1		T5	4
valid_sources[0x71]	7274	1			T2	5		T4	2		T5	5
valid_sources[0x72]	7109	1			T2	1		T5	7		T6	35
valid_sources[0x73]	11624	1			T2	1		T6	19		T7	4
valid_sources[0x74]	11818	1			T2	8		T4	1		T5	6
valid_sources[0x75]	7089	1			T2	2		T5	2		T6	21
valid_sources[0x76]	7199	1			T2	7		T5	1		T6	25
valid_sources[0x77]	8417	1			T2	4		T4	1		T5	3
valid_sources[0x78]	11600	1			T2	3		T4	1		T5	6
valid_sources[0x79]	11841	1			T1	1		T2	2		T5	4
valid_sources[0x7a]	12712	1			T2	6		T4	1		T5	3
valid_sources[0x7b]	7227	1			T2	7		T4	1		T5	3
valid_sources[0x7c]	7528	1			T2	4		T5	10		T6	33
valid_sources[0x7d]	9883	1			T2	5		T4	1		T5	3
valid_sources[0x7e]	10118	1			T2	4		T4	1		T5	6
valid_sources[0x7f]	8058	1			T2	1		T4	2		T5	4
valid_sources[0x80]	7015	1			T2	5		T5	3		T6	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1031146

1

T3

39

T4

37

T5

390

values[0x0]

all_enables

biggest_size

82102

1

T1

17

T2

216

T3

14

values[0x1]

all_enables

biggest_size

58751

1

T1

9

T2

166

T3

9