Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31719	1			T2	238		T5	7		T6	19
auto[PWRUP]	123	1			T2	2		T43	1		T55	2
auto[ONEST_0]	91	1			T2	2		T55	1		T40	2
auto[ONEST_021]	16	1			T55	2		T59	1		T231	1
auto[ONEST_1]	101	1			T2	3		T43	3		T55	4
auto[ONEST_DONE]	5	1			T56	1		T232	1		T233	1
auto[LP_0]	140	1			T2	1		T43	2		T55	3
auto[LP_021]	34	1			T2	1		T43	1		T54	1
auto[LP_1]	152	1			T2	1		T43	1		T54	2
auto[LP_EVAL]	51	1			T184	1		T56	3		T30	2
auto[LP_SLP]	551	1			T2	4		T43	7		T55	9
auto[LP_PWRUP]	29	1			T43	1		T55	1		T30	2
auto[NP_0]	202	1			T2	7		T43	5		T55	2
auto[NP_021]	31	1			T40	1		T54	1		T27	1
auto[NP_1]	200	1			T2	1		T55	2		T40	2
auto[NP_EVAL]	40	1			T43	1		T55	1		T40	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T2

1

T234

1

T58

1

min

31124

1

T2

231

T5

7

T6

19

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31141	1			T2	231		T5	7		T6	19
pow[0x1]	6	1			T56	1		T234	1		T58	1
pow[0x2]	18	1			T40	1		T30	1		T57	1
pow[0x3]	38	1			T43	2		T40	1		T56	2
pow[0x4]	80	1			T2	2		T55	1		T56	2
pow[0x5]	150	1			T2	2		T40	3		T54	3
pow[0x6]	266	1			T2	2		T43	5		T55	4
pow[0x7]	576	1			T2	6		T43	4		T55	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

230

1

T2

1

T43

4

T55

1

min

30635

1

T2

229

T5

7

T6

19

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30635	1			T2	229		T5	7		T6	19
pow[0x5]	1	1			T235	1		-	-		-	-
pow[0x7]	2	1			T236	1		T237	1		-	-
pow[0x8]	2	1			T238	1		T239	1		-	-
pow[0x9]	12	1			T56	1		T57	1		T58	1
pow[0xa]	13	1			T43	1		T54	1		T58	2
pow[0xb]	35	1			T2	2		T184	1		T30	1
pow[0xc]	79	1			T2	2		T43	1		T40	2
pow[0xd]	157	1			T43	1		T55	2		T40	4
pow[0xe]	349	1			T2	4		T43	3		T55	3
pow[0xf]	654	1			T2	7		T43	6		T55	13