Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2487	1			T2	22		T15	7		T43	8
auto[PWRUP]	158	1			T2	1		T55	2		T39	1
auto[ONEST_0]	90	1			T2	1		T43	1		T55	1
auto[ONEST_021]	19	1			T43	1		T55	1		T58	1
auto[ONEST_1]	91	1			T2	1		T55	1		T39	1
auto[ONEST_DONE]	1	1			T371	1		-	-		-	-
auto[LP_0]	147	1			T2	2		T43	1		T55	3
auto[LP_021]	41	1			T39	1		T184	1		T56	1
auto[LP_1]	143	1			T43	3		T55	2		T39	1
auto[LP_EVAL]	63	1			T55	1		T39	1		T40	1
auto[LP_SLP]	595	1			T2	7		T43	7		T55	7
auto[LP_PWRUP]	34	1			T43	1		T55	1		T54	1
auto[NP_0]	260	1			T2	2		T15	1		T43	2
auto[NP_021]	59	1			T2	2		T55	1		T40	1
auto[NP_1]	250	1			T2	4		T15	3		T43	3
auto[NP_EVAL]	39	1			T15	1		T55	1		T27	3
auto[NP_DONE]	1	1			T201	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T232

1

T88

1

T58

1

min

2080

1

T2

9

T15

12

T43

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2096	1			T2	9		T15	12		T43	9
pow[0x1]	10	1			T2	1		T17	1		T372	1
pow[0x2]	27	1			T2	1		T41	1		T54	1
pow[0x3]	55	1			T2	1		T55	2		T56	1
pow[0x4]	64	1			T2	1		T40	1		T54	1
pow[0x5]	140	1			T2	1		T43	1		T55	3
pow[0x6]	275	1			T2	3		T43	4		T55	3
pow[0x7]	619	1			T2	8		T43	4		T55	13

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T43

1

T55

1

T39

3

min

1464

1

T2

3

T15

9

T43

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1471	1			T2	3		T15	9		T43	3
pow[0x1]	16	1			T41	1		T176	1		T22	1
pow[0x2]	28	1			T15	1		T39	1		T40	1
pow[0x3]	30	1			T39	2		T18	3		T34	2
pow[0x4]	52	1			T15	2		T39	2		T17	1
pow[0x6]	2	1			T59	1		T373	1		-	-
pow[0x7]	4	1			T374	1		T351	1		T375	1
pow[0x8]	7	1			T56	1		T376	1		T377	1
pow[0x9]	12	1			T56	1		T374	1		T351	1
pow[0xa]	11	1			T34	2		T57	1		T58	1
pow[0xb]	34	1			T40	3		T56	1		T59	1
pow[0xc]	71	1			T2	1		T55	2		T39	1
pow[0xd]	183	1			T43	2		T55	4		T40	2
pow[0xe]	347	1			T2	4		T55	4		T39	2
pow[0xf]	680	1			T2	12		T43	9		T55	12