Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T5

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T7,T12,T45
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T45
0	1	Covered	T7,T12,T45
1	0	Covered	T7,T12,T45

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T10
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T10
0	1	Covered	T5,T6,T10
1	0	Covered	T5,T6,T10

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T11
0	1	Covered	T5,T6,T11
1	0	Covered	T5,T6,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T51,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T6,T7,T10
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T10
0	1	Covered	T6,T7,T10
1	0	Covered	T6,T7,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T11
0	1	Covered	T6,T10,T11
1	0	Covered	T6,T10,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T10
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T10
0	1	Covered	T5,T6,T10
1	0	Covered	T5,T6,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T11
0	1	Covered	T5,T6,T11
1	0	Covered	T5,T6,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T51,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T2,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T7,T8
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T5,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T6,T7
1	1	0	Covered	T5,T6,T7
1	1	1	Covered	T5,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T6,T7

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T8,T11
1	1	0	Covered	T6,T8,T11
1	1	1	Covered	T6,T8,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Covered	T6,T8,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T11

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Covered	T6,T8,T11
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T11

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T6,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T11,T12
1	1	0	Covered	T8,T11,T12
1	1	1	Covered	T8,T11,T12

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T12
0	1	Covered	T8,T11,T12
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T11,T12

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T12
0	1	Covered	T8,T11,T12
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T11,T12

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T6,T7,T8
1	1	0	Covered	T6,T7,T8
1	1	1	Covered	T6,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T8,T10
1	1	0	Covered	T5,T7,T8
1	1	1	Covered	T5,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T8
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T7,T8,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T8,T11

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T5,T6,T7
1	1	Covered	T8,T11,T12

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T8

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T7,T8

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T11
1	0	Covered	T6,T8,T11

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T8,T11
1	0	Covered	T6,T8,T11

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T11
1	0	Covered	T8,T11,T13
1	1	Covered	T6,T8,T11

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T12,T45

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T10

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T7

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	35105551	34762673	0	0
gen_filter_match[0].MatchCheck00_A	35105551	10732777	0	0
gen_filter_match[0].MatchCheck01_A	35105551	2840628	0	0
gen_filter_match[0].MatchCheck10_A	35105551	2621658	0	0
gen_filter_match[0].MatchCheck11_A	35105551	18567610	0	0
gen_filter_match[1].MatchCheck00_A	35105551	12788185	0	0
gen_filter_match[1].MatchCheck01_A	35105551	1591582	0	0
gen_filter_match[1].MatchCheck10_A	35105551	1282987	0	0
gen_filter_match[1].MatchCheck11_A	35105551	19099919	0	0
gen_filter_match[2].MatchCheck00_A	35105551	13096456	0	0
gen_filter_match[2].MatchCheck01_A	35105551	694192	0	0
gen_filter_match[2].MatchCheck10_A	35105551	612923	0	0
gen_filter_match[2].MatchCheck11_A	35105551	20359102	0	0
gen_filter_match[3].MatchCheck00_A	35105551	13351214	0	0
gen_filter_match[3].MatchCheck01_A	35105551	417181	0	0
gen_filter_match[3].MatchCheck10_A	35105551	300393	0	0
gen_filter_match[3].MatchCheck11_A	35105551	20693885	0	0
gen_filter_match[4].MatchCheck00_A	35105551	13479904	0	0
gen_filter_match[4].MatchCheck01_A	35105551	54032	0	0
gen_filter_match[4].MatchCheck10_A	35105551	93	0	0
gen_filter_match[4].MatchCheck11_A	35105551	21228644	0	0
gen_filter_match[5].MatchCheck00_A	35105551	13203468	0	0
gen_filter_match[5].MatchCheck01_A	35105551	64816	0	0
gen_filter_match[5].MatchCheck10_A	35105551	74007	0	0
gen_filter_match[5].MatchCheck11_A	35105551	21420382	0	0
gen_filter_match[6].MatchCheck00_A	35105551	12554537	0	0
gen_filter_match[6].MatchCheck01_A	35105551	142482	0	0
gen_filter_match[6].MatchCheck10_A	35105551	103	0	0
gen_filter_match[6].MatchCheck11_A	35105551	22065551	0	0
gen_filter_match[7].MatchCheck00_A	35105551	14079205	0	0
gen_filter_match[7].MatchCheck01_A	35105551	32885	0	0
gen_filter_match[7].MatchCheck10_A	35105551	134254	0	0
gen_filter_match[7].MatchCheck11_A	35105551	20516329	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	34762673	0	0
T1	732	646	0	0
T2	20975	17766	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	32849	0	0
T6	67742	67653	0	0
T7	32735	32659	0	0
T8	122876	122801	0	0
T9	1205	1140	0	0
T10	66204	66114	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	10732777	0	0
T1	732	646	0	0
T2	20975	17636	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	32849	0	0
T6	67742	34302	0	0
T7	32735	4	0	0
T8	122876	3	0	0
T9	1205	1140	0	0
T10	66204	32685	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	2840628	0	0
T64	71414	0	0	0
T65	0	32005	0	0
T146	1054	0	0	0
T147	578	0	0	0
T148	1085	0	0	0
T149	113664	40099	0	0
T150	65774	32327	0	0
T151	0	33449	0	0
T152	0	31786	0	0
T153	0	32523	0	0
T154	0	32983	0	0
T155	0	38193	0	0
T156	0	34142	0	0
T157	0	38630	0	0
T158	33245	0	0	0
T159	9527	0	0	0
T160	4884	0	0	0
T161	106751	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	2621658	0	0
T10	66204	33429	0	0
T11	75575	40251	0	0
T12	99111	33217	0	0
T13	116892	0	0	0
T14	39443	0	0	0
T15	16696	16051	0	0
T16	8395	0	0	0
T42	38940	0	0	0
T43	17443	0	0	0
T44	4649	0	0	0
T45	0	34767	0	0
T149	0	34777	0	0
T151	0	32449	0	0
T152	0	65525	0	0
T162	0	1	0	0
T163	0	32862	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	18567610	0	0
T2	20975	130	0	0
T3	1118	0	0	0
T4	1156	0	0	0
T5	32913	0	0	0
T6	67742	33351	0	0
T7	32735	32655	0	0
T8	122876	122798	0	0
T9	1205	0	0	0
T10	66204	0	0	0
T11	75575	0	0	0
T12	0	65833	0	0
T13	0	116807	0	0
T14	0	39368	0	0
T42	0	38853	0	0
T43	0	377	0	0
T51	0	79162	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	12788185	0	0
T1	732	646	0	0
T2	20975	17766	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	3	0	0
T6	67742	34302	0	0
T7	32735	4	0	0
T8	122876	3	0	0
T9	1205	1140	0	0
T10	66204	66114	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	1591582	0	0
T6	67742	33351	0	0
T7	32735	0	0	0
T8	122876	0	0	0
T9	1205	0	0	0
T10	66204	0	0	0
T11	75575	0	0	0
T12	99111	32443	0	0
T13	116892	0	0	0
T14	39443	0	0	0
T16	8395	0	0	0
T41	0	24658	0	0
T154	0	32093	0	0
T156	0	36450	0	0
T164	0	33448	0	0
T165	0	38999	0	0
T166	0	131516	0	0
T167	0	35715	0	0
T168	0	38513	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	1282987	0	0
T5	32913	32846	0	0
T6	67742	0	0	0
T7	32735	0	0	0
T8	122876	0	0	0
T9	1205	0	0	0
T10	66204	0	0	0
T11	75575	0	0	0
T12	99111	33390	0	0
T13	116892	0	0	0
T16	8395	0	0	0
T28	0	2	0	0
T32	0	1	0	0
T34	0	2806	0	0
T162	0	1	0	0
T169	0	33985	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	19099919	0	0
T7	32735	32655	0	0
T8	122876	122798	0	0
T9	1205	0	0	0
T10	66204	0	0	0
T11	75575	40251	0	0
T12	99111	33217	0	0
T13	116892	116807	0	0
T14	39443	39368	0	0
T15	16696	0	0	0
T16	8395	0	0	0
T42	0	38853	0	0
T51	0	79162	0	0
T52	0	64540	0	0
T53	0	38216	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	13096456	0	0
T1	732	646	0	0
T2	20975	17766	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	3	0	0
T6	67742	4	0	0
T7	32735	4	0	0
T8	122876	3	0	0
T9	1205	1140	0	0
T10	66204	33432	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	694192	0	0
T39	23638	2244	0	0
T55	22273	0	0	0
T65	70804	38699	0	0
T151	99164	0	0	0
T162	37756	0	0	0
T164	66184	0	0	0
T169	106871	0	0	0
T173	0	33113	0	0
T174	0	32899	0	0
T175	0	32379	0	0
T176	0	960	0	0
T177	0	33378	0	0
T178	0	33005	0	0
T179	0	32701	0	0
T180	0	1	0	0
T181	5187	0	0	0
T182	1165	0	0	0
T183	120743	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	612923	0	0
T28	0	2	0	0
T29	0	31993	0	0
T32	0	1	0	0
T78	72	0	0	0
T151	99164	0	0	0
T152	97385	0	0	0
T153	64820	0	0	0
T156	0	2	0	0
T162	37756	1	0	0
T163	65810	0	0	0
T165	105803	0	0	0
T170	0	2	0	0
T171	0	2	0	0
T184	0	33381	0	0
T185	0	36705	0	0
T186	0	1	0	0
T187	106451	0	0	0
T188	1163	0	0	0
T189	97265	0	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	20359102	0	0
T5	32913	32846	0	0
T6	67742	67649	0	0
T7	32735	32655	0	0
T8	122876	122798	0	0
T9	1205	0	0	0
T10	66204	32682	0	0
T11	75575	0	0	0
T12	99111	99050	0	0
T13	116892	116807	0	0
T14	0	39368	0	0
T15	0	16051	0	0
T16	8395	0	0	0
T42	0	38853	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	13351214	0	0
T1	732	646	0	0
T2	20975	17766	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	32849	0	0
T6	67742	34302	0	0
T7	32735	32659	0	0
T8	122876	3	0	0
T9	1205	1140	0	0
T10	66204	66114	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	417181	0	0
T39	23638	0	0	0
T50	0	1961	0	0
T55	22273	0	0	0
T65	70804	0	0	0
T77	67	0	0	0
T156	0	1	0	0
T157	0	34999	0	0
T161	106751	34499	0	0
T164	66184	0	0	0
T169	106871	0	0	0
T181	5187	0	0	0
T182	1165	0	0	0
T183	120743	0	0	0
T190	0	33270	0	0
T191	0	1	0	0
T192	0	36530	0	0
T193	0	1	0	0
T194	0	3099	0	0
T195	0	32431	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	300393	0	0
T28	0	3	0	0
T32	0	1	0	0
T39	23638	0	0	0
T40	0	2	0	0
T55	22273	0	0	0
T65	70804	1	0	0
T151	99164	0	0	0
T156	0	1	0	0
T162	37756	1	0	0
T164	66184	0	0	0
T169	106871	0	0	0
T171	0	2	0	0
T181	5187	0	0	0
T182	1165	0	0	0
T183	120743	0	0	0
T186	0	1	0	0
T196	0	32527	0	0
T197	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	20693885	0	0
T6	67742	33351	0	0
T7	32735	0	0	0
T8	122876	122798	0	0
T9	1205	0	0	0
T10	66204	0	0	0
T11	75575	75481	0	0
T12	99111	33217	0	0
T13	116892	116807	0	0
T14	39443	39368	0	0
T15	0	16051	0	0
T16	8395	0	0	0
T42	0	38853	0	0
T46	0	33137	0	0
T51	0	66026	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	13479904	0	0
T1	732	646	0	0
T2	20975	17766	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	32849	0	0
T6	67742	4	0	0
T7	32735	4	0	0
T8	122876	3	0	0
T9	1205	1140	0	0
T10	66204	32685	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	54032	0	0
T21	30922	20519	0	0
T118	0	1	0	0
T198	120614	3	0	0
T199	0	1	0	0
T200	0	33508	0	0
T201	2808	0	0	0
T202	98842	0	0	0
T203	66462	0	0	0
T204	31973	0	0	0
T205	25680	0	0	0
T206	1182	0	0	0
T207	98024	0	0	0
T208	79	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	93	0	0
T17	0	1	0	0
T28	0	2	0	0
T32	0	1	0	0
T40	0	2	0	0
T78	72	0	0	0
T151	99164	0	0	0
T152	97385	0	0	0
T153	64820	0	0	0
T156	0	1	0	0
T162	37756	1	0	0
T163	65810	0	0	0
T165	105803	0	0	0
T170	0	2	0	0
T171	0	2	0	0
T186	0	1	0	0
T187	106451	0	0	0
T188	1163	0	0	0
T189	97265	0	0	0
T197	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	21228644	0	0
T6	67742	67649	0	0
T7	32735	32655	0	0
T8	122876	122798	0	0
T9	1205	0	0	0
T10	66204	33429	0	0
T11	75575	40251	0	0
T12	99111	33390	0	0
T13	116892	116807	0	0
T14	39443	39368	0	0
T15	0	16051	0	0
T16	8395	0	0	0
T42	0	38853	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	13203468	0	0
T1	732	646	0	0
T2	20975	17766	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	32849	0	0
T6	67742	67653	0	0
T7	32735	32659	0	0
T8	122876	3	0	0
T9	1205	1140	0	0
T10	66204	66114	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	64816	0	0
T118	0	1	0	0
T156	107247	1	0	0
T180	0	1	0	0
T191	0	1	0	0
T199	0	1	0	0
T209	0	32289	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T213	0	32519	0	0
T214	59	0	0	0
T215	108	0	0	0
T216	38902	0	0	0
T217	109872	0	0	0
T218	1016	0	0	0
T219	612	0	0	0
T220	117296	0	0	0
T221	65911	0	0	0
T222	4559	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	74007	0	0
T39	23638	0	0	0
T40	0	2	0	0
T55	22273	0	0	0
T65	70804	1	0	0
T151	99164	0	0	0
T152	0	1	0	0
T156	0	3	0	0
T162	37756	1	0	0
T164	66184	0	0	0
T168	0	1	0	0
T169	106871	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T181	5187	0	0	0
T182	1165	0	0	0
T183	120743	0	0	0
T186	0	1	0	0
T223	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	21420382	0	0
T8	122876	122798	0	0
T9	1205	0	0	0
T10	66204	0	0	0
T11	75575	40251	0	0
T12	99111	99050	0	0
T13	116892	116807	0	0
T14	39443	39368	0	0
T15	16696	16051	0	0
T16	8395	0	0	0
T42	38940	38853	0	0
T45	0	34767	0	0
T46	0	33137	0	0
T51	0	46876	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	12554537	0	0
T1	732	646	0	0
T2	20975	17766	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	32849	0	0
T6	67742	34302	0	0
T7	32735	4	0	0
T8	122876	3	0	0
T9	1205	1140	0	0
T10	66204	3	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	142482	0	0
T64	71414	0	0	0
T65	70804	0	0	0
T77	67	0	0	0
T118	0	32458	0	0
T146	1054	0	0	0
T147	578	0	0	0
T148	1085	0	0	0
T150	65774	1	0	0
T160	4884	0	0	0
T161	106751	0	0	0
T170	0	1	0	0
T181	5187	0	0	0
T199	0	1	0	0
T211	0	1	0	0
T212	0	1	0	0
T224	0	34037	0	0
T225	0	38355	0	0
T226	0	1	0	0
T227	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	103	0	0
T12	99111	1	0	0
T13	116892	0	0	0
T14	39443	0	0	0
T15	16696	0	0	0
T16	8395	0	0	0
T28	0	2	0	0
T42	38940	0	0	0
T43	17443	0	0	0
T44	4649	0	0	0
T45	34831	0	0	0
T46	33197	0	0	0
T65	0	1	0	0
T156	0	2	0	0
T162	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T186	0	1	0	0
T223	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	22065551	0	0
T6	67742	33351	0	0
T7	32735	32655	0	0
T8	122876	122798	0	0
T9	1205	0	0	0
T10	66204	66111	0	0
T11	75575	75481	0	0
T12	99111	32442	0	0
T13	116892	116807	0	0
T14	39443	39368	0	0
T15	0	16051	0	0
T16	8395	0	0	0
T42	0	38853	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	14079205	0	0
T1	732	646	0	0
T2	20975	17766	0	0
T3	1118	1067	0	0
T4	1156	1106	0	0
T5	32913	3	0	0
T6	67742	67653	0	0
T7	32735	4	0	0
T8	122876	3	0	0
T9	1205	1140	0	0
T10	66204	33432	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	32885	0	0
T64	71414	0	0	0
T65	70804	0	0	0
T77	67	0	0	0
T89	0	32868	0	0
T118	0	2	0	0
T146	1054	0	0	0
T147	578	0	0	0
T148	1085	0	0	0
T150	65774	1	0	0
T152	0	1	0	0
T156	0	2	0	0
T160	4884	0	0	0
T161	106751	0	0	0
T180	0	1	0	0
T181	5187	0	0	0
T191	0	1	0	0
T198	0	3	0	0
T228	0	1	0	0
T229	0	1	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	134254	0	0
T5	32913	1	0	0
T6	67742	0	0	0
T7	32735	0	0	0
T8	122876	0	0	0
T9	1205	0	0	0
T10	66204	0	0	0
T11	75575	0	0	0
T12	99111	0	0	0
T13	116892	0	0	0
T16	8395	0	0	0
T65	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0
T156	0	2	0	0
T162	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T221	0	1	0	0
T223	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35105551	20516329	0	0
T5	32913	32845	0	0
T6	67742	0	0	0
T7	32735	32655	0	0
T8	122876	122798	0	0
T9	1205	0	0	0
T10	66204	32682	0	0
T11	75575	0	0	0
T12	99111	66607	0	0
T13	116892	116807	0	0
T14	0	39368	0	0
T16	8395	0	0	0
T42	0	38853	0	0
T45	0	34767	0	0
T51	0	32286	0	0