Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1495	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1555	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1412	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1446	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1589	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1293	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1464	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1628	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1493	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1426	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1513	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1310	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1487	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1427	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1388	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1474	0	0
adc_en_ctl_rd_A	2147483647	1154	0	0
adc_fsm_rst_rd_A	2147483647	1092	0	0
adc_intr_ctl_rd_A	2147483647	1612	0	0
adc_lp_sample_ctl_rd_A	2147483647	1102	0	0
adc_pd_ctl_rd_A	2147483647	1305	0	0
adc_sample_ctl_rd_A	2147483647	1063	0	0
adc_wakeup_ctl_rd_A	2147483647	1172	0	0
intr_enable_rd_A	2147483647	1659	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1495	0	0
T17	700515	5	0	0
T18	470828	10	0	0
T19	0	23	0	0
T20	0	7	0	0
T21	0	30	0	0
T22	0	47	0	0
T23	0	26	0	0
T24	0	41	0	0
T25	0	64	0	0
T26	0	23	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1555	0	0
T17	700515	21	0	0
T18	470828	26	0	0
T19	0	24	0	0
T20	0	12	0	0
T21	0	18	0	0
T22	0	35	0	0
T23	0	19	0	0
T24	0	26	0	0
T25	0	46	0	0
T26	0	17	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1412	0	0
T17	700515	23	0	0
T18	470828	8	0	0
T19	0	28	0	0
T20	0	1	0	0
T21	0	37	0	0
T22	0	40	0	0
T23	0	18	0	0
T24	0	36	0	0
T25	0	22	0	0
T26	0	13	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1446	0	0
T17	700515	13	0	0
T18	470828	21	0	0
T19	0	17	0	0
T20	0	5	0	0
T21	0	18	0	0
T22	0	49	0	0
T23	0	26	0	0
T24	0	15	0	0
T25	0	28	0	0
T26	0	20	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1589	0	0
T17	700515	27	0	0
T18	470828	34	0	0
T19	0	21	0	0
T20	0	32	0	0
T21	0	5	0	0
T22	0	40	0	0
T23	0	32	0	0
T24	0	24	0	0
T25	0	17	0	0
T26	0	25	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1293	0	0
T17	700515	35	0	0
T18	470828	13	0	0
T19	0	26	0	0
T20	0	6	0	0
T21	0	16	0	0
T22	0	17	0	0
T23	0	20	0	0
T24	0	42	0	0
T25	0	31	0	0
T26	0	17	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1464	0	0
T17	700515	21	0	0
T18	470828	20	0	0
T19	0	20	0	0
T20	0	14	0	0
T21	0	24	0	0
T22	0	26	0	0
T23	0	22	0	0
T24	0	37	0	0
T25	0	39	0	0
T26	0	10	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1628	0	0
T17	700515	24	0	0
T18	470828	30	0	0
T19	0	18	0	0
T20	0	10	0	0
T21	0	17	0	0
T22	0	26	0	0
T23	0	28	0	0
T24	0	40	0	0
T25	0	47	0	0
T26	0	26	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1493	0	0
T17	700515	17	0	0
T18	470828	17	0	0
T19	0	26	0	0
T20	0	7	0	0
T21	0	7	0	0
T22	0	26	0	0
T23	0	24	0	0
T24	0	50	0	0
T25	0	25	0	0
T26	0	26	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1426	0	0
T17	700515	16	0	0
T18	470828	15	0	0
T19	0	12	0	0
T20	0	4	0	0
T21	0	21	0	0
T22	0	21	0	0
T23	0	31	0	0
T24	0	45	0	0
T25	0	28	0	0
T26	0	6	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513	0	0
T17	700515	19	0	0
T18	470828	17	0	0
T19	0	25	0	0
T20	0	1	0	0
T21	0	22	0	0
T22	0	53	0	0
T23	0	11	0	0
T24	0	39	0	0
T25	0	16	0	0
T26	0	8	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1310	0	0
T17	700515	17	0	0
T18	470828	30	0	0
T19	0	22	0	0
T20	0	4	0	0
T21	0	1	0	0
T22	0	36	0	0
T23	0	25	0	0
T24	0	32	0	0
T25	0	22	0	0
T26	0	28	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1487	0	0
T17	700515	18	0	0
T18	470828	26	0	0
T19	0	12	0	0
T20	0	1	0	0
T21	0	10	0	0
T22	0	38	0	0
T23	0	26	0	0
T24	0	42	0	0
T25	0	51	0	0
T26	0	11	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1427	0	0
T17	700515	14	0	0
T18	470828	32	0	0
T19	0	9	0	0
T20	0	19	0	0
T21	0	9	0	0
T22	0	44	0	0
T23	0	18	0	0
T24	0	33	0	0
T25	0	35	0	0
T26	0	8	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1388	0	0
T17	700515	14	0	0
T18	470828	36	0	0
T19	0	19	0	0
T20	0	9	0	0
T21	0	16	0	0
T22	0	57	0	0
T23	0	12	0	0
T24	0	36	0	0
T25	0	25	0	0
T26	0	15	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1474	0	0
T17	700515	20	0	0
T18	470828	16	0	0
T19	0	14	0	0
T21	0	20	0	0
T22	0	45	0	0
T23	0	11	0	0
T24	0	30	0	0
T25	0	23	0	0
T26	0	21	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0
T35	0	12	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1154	0	0
T17	700515	10	0	0
T18	470828	17	0	0
T19	0	14	0	0
T20	0	6	0	0
T21	0	24	0	0
T22	0	43	0	0
T23	0	26	0	0
T24	0	25	0	0
T25	0	19	0	0
T26	0	17	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1092	0	0
T17	700515	19	0	0
T18	470828	19	0	0
T19	0	19	0	0
T20	0	2	0	0
T21	0	5	0	0
T22	0	39	0	0
T23	0	24	0	0
T24	0	37	0	0
T25	0	44	0	0
T26	0	20	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1612	0	0
T17	700515	16	0	0
T18	470828	22	0	0
T19	0	21	0	0
T20	0	5	0	0
T21	0	10	0	0
T22	0	44	0	0
T23	0	25	0	0
T24	0	36	0	0
T25	0	40	0	0
T26	0	14	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1102	0	0
T17	700515	20	0	0
T18	470828	24	0	0
T19	0	29	0	0
T20	0	8	0	0
T21	0	33	0	0
T22	0	38	0	0
T23	0	16	0	0
T24	0	44	0	0
T25	0	28	0	0
T26	0	20	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1305	0	0
T17	700515	19	0	0
T18	470828	30	0	0
T19	0	19	0	0
T20	0	6	0	0
T21	0	25	0	0
T22	0	31	0	0
T23	0	18	0	0
T24	0	34	0	0
T25	0	33	0	0
T26	0	9	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1063	0	0
T17	700515	14	0	0
T18	470828	9	0	0
T19	0	13	0	0
T20	0	25	0	0
T21	0	2	0	0
T22	0	38	0	0
T23	0	10	0	0
T24	0	40	0	0
T25	0	36	0	0
T26	0	25	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1172	0	0
T17	700515	8	0	0
T18	470828	9	0	0
T19	0	24	0	0
T20	0	10	0	0
T21	0	14	0	0
T22	0	35	0	0
T23	0	16	0	0
T24	0	28	0	0
T25	0	37	0	0
T26	0	20	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1659	0	0
T17	700515	31	0	0
T18	470828	33	0	0
T19	0	33	0	0
T20	0	9	0	0
T21	0	43	0	0
T22	0	51	0	0
T23	0	31	0	0
T27	702992	0	0	0
T28	191717	0	0	0
T29	314329	0	0	0
T30	903203	0	0	0
T31	168403	0	0	0
T32	583437	0	0	0
T33	385416	0	0	0
T34	248637	0	0	0
T36	0	10	0	0
T37	0	17	0	0
T38	0	11	0	0