Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1164017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1139507

1

T1

4283

T4

2

T2

492

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2006008	1			T1	8139		T4	1		T2	861
values[0x0]	148669	1			T1	250		T4	3		T2	50
values[0x1]	148847	1			T1	262		T4	3		T2	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	932229	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1371295

1

T1

5171

T4

3

T2

586

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7119	1			T1	39		T2	3		T5	8
valid_sources[0x01]	6931	1			T1	47		T2	8		T5	10
valid_sources[0x02]	20046	1			T1	32		T2	8		T5	9
valid_sources[0x03]	7022	1			T1	41		T2	9		T5	8
valid_sources[0x04]	8496	1			T1	47		T2	7		T5	13
valid_sources[0x05]	7201	1			T1	39		T2	4		T5	13
valid_sources[0x06]	6828	1			T1	26		T2	2		T5	20
valid_sources[0x07]	7164	1			T1	48		T2	1		T3	4
valid_sources[0x08]	7127	1			T1	24		T5	10		T6	14
valid_sources[0x09]	6969	1			T1	43		T2	5		T5	20
valid_sources[0x0a]	7048	1			T1	35		T2	9		T5	10
valid_sources[0x0b]	11785	1			T1	32		T2	10		T5	15
valid_sources[0x0c]	7096	1			T1	27		T2	4		T5	14
valid_sources[0x0d]	10735	1			T1	23		T2	1		T5	13
valid_sources[0x0e]	9558	1			T1	18		T2	4		T5	6
valid_sources[0x0f]	10932	1			T1	32		T2	1		T5	15
valid_sources[0x10]	7617	1			T1	29		T2	1		T5	13
valid_sources[0x11]	6675	1			T1	39		T2	3		T5	7
valid_sources[0x12]	6927	1			T1	45		T2	3		T5	11
valid_sources[0x13]	12195	1			T1	46		T5	11		T6	9
valid_sources[0x14]	9280	1			T1	28		T2	1		T5	10
valid_sources[0x15]	9924	1			T1	51		T2	8		T5	14
valid_sources[0x16]	11775	1			T1	38		T2	3		T5	15
valid_sources[0x17]	6958	1			T1	15		T5	17		T6	9
valid_sources[0x18]	7442	1			T1	29		T2	1		T5	10
valid_sources[0x19]	8030	1			T1	34		T2	8		T5	15
valid_sources[0x1a]	7429	1			T1	43		T2	11		T5	7
valid_sources[0x1b]	6768	1			T1	41		T2	3		T5	20
valid_sources[0x1c]	7192	1			T1	26		T5	11		T6	2
valid_sources[0x1d]	10609	1			T1	37		T2	5		T5	8
valid_sources[0x1e]	7038	1			T1	30		T2	2		T5	5
valid_sources[0x1f]	11132	1			T1	45		T2	11		T5	16
valid_sources[0x20]	11077	1			T1	17		T2	1		T5	12
valid_sources[0x21]	11189	1			T1	24		T5	12		T6	11
valid_sources[0x22]	6934	1			T1	39		T2	9		T5	11
valid_sources[0x23]	7534	1			T1	35		T2	9		T5	4
valid_sources[0x24]	6679	1			T1	51		T2	4		T5	15
valid_sources[0x25]	11736	1			T1	29		T2	10		T5	14
valid_sources[0x26]	7008	1			T1	18		T2	3		T5	12
valid_sources[0x27]	7603	1			T1	26		T2	1		T5	10
valid_sources[0x28]	7391	1			T1	42		T2	4		T5	6
valid_sources[0x29]	7742	1			T1	33		T2	5		T5	8
valid_sources[0x2a]	9842	1			T1	36		T2	1		T5	12
valid_sources[0x2b]	11484	1			T1	26		T2	5		T5	9
valid_sources[0x2c]	10877	1			T1	24		T2	3		T3	5
valid_sources[0x2d]	11674	1			T1	28		T5	9		T6	14
valid_sources[0x2e]	7134	1			T1	30		T2	1		T5	16
valid_sources[0x2f]	6819	1			T1	35		T2	5		T5	15
valid_sources[0x30]	7710	1			T1	42		T2	7		T5	12
valid_sources[0x31]	10690	1			T1	30		T2	9		T5	5
valid_sources[0x32]	12573	1			T1	37		T2	6		T5	21
valid_sources[0x33]	6772	1			T1	21		T2	9		T5	18
valid_sources[0x34]	6630	1			T1	32		T2	1		T5	8
valid_sources[0x35]	11106	1			T1	27		T2	10		T5	3
valid_sources[0x36]	13986	1			T1	22		T2	4		T5	6
valid_sources[0x37]	7820	1			T1	32		T2	4		T5	10
valid_sources[0x38]	6969	1			T1	29		T2	4		T5	9
valid_sources[0x39]	6946	1			T1	22		T5	12		T6	28
valid_sources[0x3a]	11660	1			T1	39		T2	6		T5	11
valid_sources[0x3b]	9629	1			T1	37		T2	1		T5	13
valid_sources[0x3c]	6724	1			T1	33		T2	3		T5	17
valid_sources[0x3d]	8405	1			T1	33		T2	5		T5	24
valid_sources[0x3e]	15204	1			T1	39		T2	7		T5	7
valid_sources[0x3f]	8666	1			T1	35		T5	13		T6	4
valid_sources[0x40]	11265	1			T1	38		T5	20		T6	17
valid_sources[0x41]	6668	1			T1	26		T5	11		T6	12
valid_sources[0x42]	6731	1			T1	33		T2	4		T5	8
valid_sources[0x43]	11408	1			T1	33		T2	8		T5	12
valid_sources[0x44]	6928	1			T1	45		T5	17		T6	10
valid_sources[0x45]	7959	1			T1	37		T2	1		T5	10
valid_sources[0x46]	10869	1			T1	33		T2	10		T5	12
valid_sources[0x47]	6684	1			T1	56		T2	5		T5	6
valid_sources[0x48]	7618	1			T1	59		T5	14		T6	16
valid_sources[0x49]	11523	1			T1	36		T2	2		T5	14
valid_sources[0x4a]	6691	1			T1	23		T2	1		T5	14
valid_sources[0x4b]	7742	1			T1	37		T5	26		T6	16
valid_sources[0x4c]	6880	1			T1	36		T2	1		T5	9
valid_sources[0x4d]	10654	1			T1	20		T3	2		T5	12
valid_sources[0x4e]	11078	1			T1	34		T5	14		T6	7
valid_sources[0x4f]	7721	1			T1	36		T2	5		T5	8
valid_sources[0x50]	16545	1			T1	37		T2	1		T5	13
valid_sources[0x51]	14044	1			T1	23		T2	13		T5	22
valid_sources[0x52]	6802	1			T1	26		T2	6		T5	16
valid_sources[0x53]	7084	1			T1	36		T2	2		T5	23
valid_sources[0x54]	6974	1			T1	21		T2	2		T5	6
valid_sources[0x55]	8112	1			T1	27		T2	3		T5	15
valid_sources[0x56]	7400	1			T1	31		T2	3		T5	13
valid_sources[0x57]	6936	1			T1	47		T2	6		T5	6
valid_sources[0x58]	8146	1			T1	36		T2	8		T5	11
valid_sources[0x59]	7042	1			T1	24		T2	1		T5	13
valid_sources[0x5a]	7004	1			T1	37		T5	12		T6	11
valid_sources[0x5b]	11422	1			T1	39		T2	1		T5	16
valid_sources[0x5c]	10822	1			T1	38		T2	4		T5	11
valid_sources[0x5d]	11673	1			T1	39		T2	1		T5	14
valid_sources[0x5e]	10550	1			T1	40		T2	3		T5	8
valid_sources[0x5f]	7446	1			T1	31		T2	1		T5	8
valid_sources[0x60]	7213	1			T1	22		T2	4		T5	11
valid_sources[0x61]	9371	1			T1	30		T2	2		T5	11
valid_sources[0x62]	11349	1			T1	34		T2	4		T5	22
valid_sources[0x63]	6886	1			T1	36		T2	4		T5	11
valid_sources[0x64]	8976	1			T1	26		T2	3		T5	11
valid_sources[0x65]	7149	1			T1	29		T2	5		T3	6
valid_sources[0x66]	8547	1			T1	38		T2	5		T5	11
valid_sources[0x67]	7511	1			T1	56		T2	1		T5	11
valid_sources[0x68]	9302	1			T1	24		T2	6		T5	3
valid_sources[0x69]	7111	1			T1	35		T2	7		T5	8
valid_sources[0x6a]	7258	1			T1	25		T2	3		T5	9
valid_sources[0x6b]	7245	1			T1	31		T2	9		T5	5
valid_sources[0x6c]	9076	1			T1	28		T2	2		T5	13
valid_sources[0x6d]	7138	1			T1	52		T2	8		T5	8
valid_sources[0x6e]	12243	1			T1	26		T2	2		T5	8
valid_sources[0x6f]	9751	1			T1	34		T2	3		T5	11
valid_sources[0x70]	6977	1			T1	36		T2	14		T5	7
valid_sources[0x71]	11284	1			T1	47		T2	4		T5	24
valid_sources[0x72]	6929	1			T1	33		T2	6		T5	10
valid_sources[0x73]	8202	1			T1	47		T2	2		T5	21
valid_sources[0x74]	11486	1			T1	40		T2	12		T5	22
valid_sources[0x75]	6823	1			T1	30		T2	6		T5	4
valid_sources[0x76]	9720	1			T1	32		T2	5		T5	15
valid_sources[0x77]	7578	1			T1	19		T2	3		T5	14
valid_sources[0x78]	8039	1			T1	29		T2	1		T5	5
valid_sources[0x79]	9470	1			T1	23		T2	1		T5	4
valid_sources[0x7a]	6598	1			T1	26		T2	6		T5	8
valid_sources[0x7b]	6699	1			T1	43		T2	4		T5	15
valid_sources[0x7c]	7356	1			T1	27		T2	7		T5	14
valid_sources[0x7d]	6928	1			T1	36		T2	2		T5	14
valid_sources[0x7e]	12682	1			T1	46		T2	6		T5	21
valid_sources[0x7f]	11512	1			T1	34		T2	3		T5	18
valid_sources[0x80]	11090	1			T1	30		T2	1		T5	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

999877

1

T1

4094

T2

436

T5

1301

values[0x0]

all_enables

biggest_size

81001

1

T1

118

T4

2

T2

31

values[0x1]

all_enables

biggest_size

58629

1

T1

71

T2

25

T3

11