Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31877	1			T1	12		T2	8		T5	24
auto[PWRUP]	116	1			T43	2		T33	1		T42	2
auto[ONEST_0]	73	1			T47	1		T201	1		T136	2
auto[ONEST_021]	20	1			T48	1		T136	1		T35	2
auto[ONEST_1]	62	1			T42	1		T201	1		T136	3
auto[ONEST_DONE]	2	1			T202	1		T203	1		-	-
auto[LP_0]	151	1			T14	1		T33	2		T44	5
auto[LP_021]	34	1			T43	1		T201	1		T48	1
auto[LP_1]	133	1			T14	1		T33	1		T42	1
auto[LP_EVAL]	64	1			T42	1		T37	1		T44	1
auto[LP_SLP]	543	1			T14	1		T43	7		T33	5
auto[LP_PWRUP]	28	1			T42	1		T44	1		T201	1
auto[NP_0]	173	1			T43	1		T33	3		T42	3
auto[NP_021]	42	1			T43	1		T44	1		T201	1
auto[NP_1]	161	1			T43	3		T33	1		T42	3
auto[NP_EVAL]	37	1			T47	1		T134	1		T136	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T43

1

T44

1

T48

1

min

31373

1

T1

12

T2

8

T5

24

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	31383	1			T1	12		T2	8		T5	24
pow[0x1]	7	1			T45	1		T204	1		T205	1
pow[0x2]	9	1			T45	1		T206	1		T207	1
pow[0x3]	26	1			T201	1		T136	1		T34	1
pow[0x4]	60	1			T43	1		T44	1		T47	1
pow[0x5]	130	1			T42	2		T44	2		T201	2
pow[0x6]	296	1			T14	1		T43	2		T33	3
pow[0x7]	561	1			T14	1		T43	6		T33	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

186

1

T43

2

T33

2

T42

3

min

30865

1

T1

12

T2

8

T5

24

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30865	1			T1	12		T2	8		T5	24
pow[0x5]	1	1			T45	1		-	-		-	-
pow[0x6]	2	1			T34	1		T208	1		-	-
pow[0x7]	2	1			T47	1		T98	1		-	-
pow[0x8]	5	1			T42	1		T209	1		T202	1
pow[0x9]	11	1			T43	1		T42	1		T44	1
pow[0xa]	23	1			T48	1		T210	1		T207	1
pow[0xb]	30	1			T43	1		T33	1		T44	2
pow[0xc]	76	1			T43	1		T42	1		T44	2
pow[0xd]	137	1			T43	1		T33	1		T42	2
pow[0xe]	319	1			T43	4		T33	5		T42	4
pow[0xf]	659	1			T43	8		T33	2		T42	5