Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2410	1			T7	5		T13	3		T14	12
auto[PWRUP]	142	1			T36	1		T33	1		T42	3
auto[ONEST_0]	86	1			T14	1		T33	1		T42	2
auto[ONEST_021]	22	1			T42	1		T47	1		T48	1
auto[ONEST_1]	82	1			T43	1		T33	2		T134	2
auto[ONEST_DONE]	4	1			T43	1		T37	1		T307	1
auto[LP_0]	147	1			T14	1		T43	2		T33	2
auto[LP_021]	40	1			T44	1		T38	1		T201	1
auto[LP_1]	130	1			T43	1		T33	1		T42	5
auto[LP_EVAL]	70	1			T14	2		T43	2		T33	1
auto[LP_SLP]	596	1			T14	3		T36	2		T43	5
auto[LP_PWRUP]	31	1			T33	1		T44	1		T38	1
auto[NP_0]	215	1			T33	4		T42	4		T37	2
auto[NP_021]	57	1			T14	2		T43	1		T33	1
auto[NP_1]	255	1			T14	3		T36	1		T43	1
auto[NP_EVAL]	46	1			T33	2		T37	1		T329	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T330

1

T331

1

T332

1

min

2064

1

T7

5

T13

3

T14

18

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2071	1			T7	5		T13	3		T14	18
pow[0x1]	7	1			T134	1		T46	1		T331	1
pow[0x2]	21	1			T33	2		T42	2		T204	1
pow[0x3]	41	1			T47	1		T38	1		T201	1
pow[0x4]	85	1			T14	1		T42	1		T44	1
pow[0x5]	130	1			T14	1		T43	1		T33	1
pow[0x6]	283	1			T43	4		T33	4		T42	6
pow[0x7]	587	1			T14	1		T43	6		T33	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

204

1

T43

1

T33

4

T42

2

min

1409

1

T7

5

T13

3

T14

13

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1414	1			T7	5		T13	3		T14	13
pow[0x1]	18	1			T14	1		T38	1		T333	2
pow[0x2]	33	1			T33	1		T37	1		T39	1
pow[0x3]	41	1			T14	1		T15	2		T40	4
pow[0x4]	46	1			T14	2		T33	2		T38	5
pow[0x5]	1	1			T207	1		-	-		-	-
pow[0x6]	1	1			T334	1		-	-		-	-
pow[0x7]	1	1			T335	1		-	-		-	-
pow[0x8]	5	1			T223	1		T336	1		T337	1
pow[0x9]	13	1			T47	1		T45	1		T249	1
pow[0xa]	15	1			T329	1		T46	1		T331	1
pow[0xb]	29	1			T136	2		T34	1		T204	2
pow[0xc]	84	1			T14	1		T42	4		T44	2
pow[0xd]	159	1			T14	2		T33	1		T42	2
pow[0xe]	308	1			T14	1		T43	2		T33	3
pow[0xf]	665	1			T14	1		T43	8		T33	6