Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2691	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2737	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2663	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2551	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2422	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2734	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2562	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2539	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2302	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2625	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2525	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2394	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2562	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2808	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2634	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2646	0	0
adc_en_ctl_rd_A	2147483647	2284	0	0
adc_fsm_rst_rd_A	2147483647	2055	0	0
adc_intr_ctl_rd_A	2147483647	2488	0	0
adc_lp_sample_ctl_rd_A	2147483647	2033	0	0
adc_pd_ctl_rd_A	2147483647	2360	0	0
adc_sample_ctl_rd_A	2147483647	2036	0	0
adc_wakeup_ctl_rd_A	2147483647	2199	0	0
intr_enable_rd_A	2147483647	2725	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2691	0	0
T14	793785	50	0	0
T15	0	29	0	0
T16	0	34	0	0
T17	0	19	0	0
T18	0	21	0	0
T19	0	18	0	0
T20	0	42	0	0
T21	0	33	0	0
T22	0	22	0	0
T23	0	32	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2737	0	0
T14	793785	31	0	0
T15	0	67	0	0
T16	0	22	0	0
T17	0	14	0	0
T18	0	14	0	0
T19	0	23	0	0
T20	0	46	0	0
T21	0	12	0	0
T22	0	19	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	23	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2663	0	0
T14	793785	46	0	0
T15	0	42	0	0
T16	0	37	0	0
T17	0	15	0	0
T18	0	25	0	0
T19	0	24	0	0
T20	0	19	0	0
T21	0	30	0	0
T22	0	14	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	11	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2551	0	0
T14	793785	49	0	0
T15	0	39	0	0
T16	0	14	0	0
T17	0	12	0	0
T18	0	7	0	0
T19	0	23	0	0
T20	0	36	0	0
T21	0	11	0	0
T22	0	14	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	13	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2422	0	0
T14	793785	39	0	0
T15	0	39	0	0
T16	0	14	0	0
T17	0	15	0	0
T18	0	28	0	0
T19	0	17	0	0
T20	0	31	0	0
T21	0	17	0	0
T22	0	8	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	16	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2734	0	0
T14	793785	55	0	0
T15	0	47	0	0
T16	0	10	0	0
T17	0	9	0	0
T18	0	24	0	0
T19	0	16	0	0
T20	0	40	0	0
T21	0	30	0	0
T22	0	10	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	19	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2562	0	0
T14	793785	57	0	0
T15	0	30	0	0
T16	0	13	0	0
T17	0	7	0	0
T18	0	27	0	0
T19	0	26	0	0
T20	0	54	0	0
T21	0	17	0	0
T22	0	8	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	27	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2539	0	0
T14	793785	29	0	0
T15	0	47	0	0
T16	0	18	0	0
T17	0	12	0	0
T18	0	17	0	0
T19	0	17	0	0
T20	0	30	0	0
T21	0	25	0	0
T22	0	7	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	25	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2302	0	0
T14	793785	39	0	0
T15	0	32	0	0
T16	0	17	0	0
T17	0	15	0	0
T18	0	11	0	0
T19	0	17	0	0
T20	0	41	0	0
T21	0	24	0	0
T22	0	20	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	3	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2625	0	0
T14	793785	32	0	0
T15	0	48	0	0
T16	0	11	0	0
T17	0	14	0	0
T18	0	24	0	0
T19	0	17	0	0
T20	0	52	0	0
T21	0	24	0	0
T22	0	18	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	26	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2525	0	0
T14	793785	31	0	0
T15	0	52	0	0
T16	0	8	0	0
T17	0	8	0	0
T18	0	21	0	0
T19	0	31	0	0
T20	0	31	0	0
T21	0	29	0	0
T22	0	15	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	35	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2394	0	0
T14	793785	47	0	0
T15	0	61	0	0
T16	0	21	0	0
T17	0	3	0	0
T18	0	6	0	0
T19	0	20	0	0
T20	0	18	0	0
T21	0	23	0	0
T22	0	10	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	21	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2562	0	0
T14	793785	38	0	0
T15	0	38	0	0
T16	0	10	0	0
T17	0	19	0	0
T18	0	9	0	0
T19	0	25	0	0
T20	0	31	0	0
T21	0	27	0	0
T22	0	16	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	22	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2808	0	0
T14	793785	42	0	0
T15	0	40	0	0
T16	0	18	0	0
T17	0	2	0	0
T18	0	7	0	0
T19	0	17	0	0
T20	0	47	0	0
T21	0	16	0	0
T22	0	13	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	25	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2634	0	0
T14	793785	45	0	0
T15	0	37	0	0
T16	0	23	0	0
T17	0	2	0	0
T18	0	34	0	0
T19	0	21	0	0
T20	0	25	0	0
T21	0	25	0	0
T22	0	19	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	3	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2646	0	0
T14	793785	30	0	0
T15	0	36	0	0
T16	0	26	0	0
T17	0	7	0	0
T18	0	4	0	0
T19	0	23	0	0
T20	0	43	0	0
T21	0	21	0	0
T22	0	15	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	11	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2284	0	0
T14	793785	31	0	0
T15	0	32	0	0
T16	0	20	0	0
T17	0	5	0	0
T18	0	28	0	0
T19	0	21	0	0
T20	0	37	0	0
T21	0	23	0	0
T22	0	15	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	25	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2055	0	0
T14	793785	40	0	0
T15	0	48	0	0
T16	0	28	0	0
T17	0	14	0	0
T18	0	16	0	0
T19	0	8	0	0
T20	0	42	0	0
T21	0	22	0	0
T22	0	14	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	16	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2488	0	0
T14	793785	29	0	0
T15	0	50	0	0
T16	0	6	0	0
T17	0	18	0	0
T18	0	20	0	0
T19	0	24	0	0
T20	0	48	0	0
T21	0	8	0	0
T22	0	6	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	21	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2033	0	0
T14	793785	33	0	0
T15	0	48	0	0
T16	0	18	0	0
T18	0	8	0	0
T19	0	33	0	0
T20	0	46	0	0
T21	0	18	0	0
T22	0	11	0	0
T23	0	30	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	24	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2360	0	0
T14	793785	37	0	0
T15	0	37	0	0
T16	0	26	0	0
T17	0	17	0	0
T18	0	16	0	0
T19	0	24	0	0
T20	0	39	0	0
T21	0	13	0	0
T22	0	13	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	6	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2036	0	0
T14	793785	31	0	0
T15	0	46	0	0
T16	0	12	0	0
T17	0	4	0	0
T18	0	14	0	0
T19	0	15	0	0
T20	0	54	0	0
T21	0	21	0	0
T22	0	13	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	23	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2199	0	0
T14	793785	39	0	0
T15	0	33	0	0
T16	0	23	0	0
T17	0	10	0	0
T18	0	19	0	0
T19	0	19	0	0
T20	0	37	0	0
T21	0	17	0	0
T22	0	9	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2725	0	0
T14	793785	41	0	0
T15	0	27	0	0
T16	0	27	0	0
T17	0	8	0	0
T18	0	11	0	0
T19	0	38	0	0
T20	0	72	0	0
T24	121251	0	0	0
T25	553840	0	0	0
T26	125888	0	0	0
T27	160823	0	0	0
T28	166865	0	0	0
T29	569297	0	0	0
T30	155528	0	0	0
T31	590469	0	0	0
T32	572754	0	0	0
T33	0	17	0	0
T34	0	5	0	0
T35	0	12	0	0