Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1187292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1159393

1

T1

475

T2

1418

T3

916

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2065606	1			T1	852		T2	2545		T3	1685
values[0x0]	139990	1			T1	42		T2	163		T3	87
values[0x1]	141089	1			T1	45		T2	139		T3	98

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	949372	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1397313

1

T1

562

T2

1720

T3

1108

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8334	1			T2	17		T3	8		T4	37
valid_sources[0x01]	7429	1			T1	2		T2	17		T3	3
valid_sources[0x02]	13926	1			T1	4		T2	11		T3	8
valid_sources[0x03]	8497	1			T1	2		T2	11		T3	15
valid_sources[0x04]	7340	1			T1	4		T2	11		T3	9
valid_sources[0x05]	7281	1			T1	3		T2	33		T3	6
valid_sources[0x06]	8153	1			T2	8		T3	7		T4	35
valid_sources[0x07]	7219	1			T1	4		T2	6		T3	30
valid_sources[0x08]	7311	1			T1	2		T2	15		T3	2
valid_sources[0x09]	15666	1			T1	2		T2	17		T3	16
valid_sources[0x0a]	7397	1			T1	2		T2	13		T3	9
valid_sources[0x0b]	7226	1			T1	2		T2	4		T3	1
valid_sources[0x0c]	7261	1			T1	6		T2	5		T3	9
valid_sources[0x0d]	11253	1			T1	2		T2	8		T4	30
valid_sources[0x0e]	7952	1			T1	4		T2	10		T3	6
valid_sources[0x0f]	6925	1			T1	5		T2	4		T3	2
valid_sources[0x10]	7258	1			T1	5		T2	4		T3	2
valid_sources[0x11]	8390	1			T1	6		T2	6		T3	1
valid_sources[0x12]	8500	1			T1	10		T2	10		T3	10
valid_sources[0x13]	7941	1			T1	3		T2	14		T3	2
valid_sources[0x14]	7494	1			T1	2		T2	26		T3	18
valid_sources[0x15]	11615	1			T1	3		T2	11		T3	17
valid_sources[0x16]	12397	1			T1	6		T2	15		T4	37
valid_sources[0x17]	7263	1			T1	5		T2	8		T3	13
valid_sources[0x18]	15065	1			T1	4		T2	13		T3	7
valid_sources[0x19]	13016	1			T1	4		T2	9		T3	15
valid_sources[0x1a]	9583	1			T2	17		T3	14		T4	34
valid_sources[0x1b]	7236	1			T1	5		T2	6		T3	9
valid_sources[0x1c]	7381	1			T1	2		T2	7		T3	10
valid_sources[0x1d]	10515	1			T1	1		T2	14		T4	41
valid_sources[0x1e]	7232	1			T1	6		T2	5		T3	7
valid_sources[0x1f]	6898	1			T1	3		T2	4		T3	3
valid_sources[0x20]	7534	1			T1	3		T2	14		T3	7
valid_sources[0x21]	7079	1			T1	5		T2	4		T3	12
valid_sources[0x22]	9017	1			T1	5		T2	17		T3	5
valid_sources[0x23]	7574	1			T1	5		T2	9		T3	1
valid_sources[0x24]	11415	1			T1	4		T2	9		T3	5
valid_sources[0x25]	7319	1			T1	5		T2	13		T3	13
valid_sources[0x26]	8583	1			T1	5		T2	8		T3	7
valid_sources[0x27]	10366	1			T1	6		T2	13		T3	10
valid_sources[0x28]	11652	1			T1	2		T2	13		T3	4
valid_sources[0x29]	7807	1			T1	1		T2	5		T3	7
valid_sources[0x2a]	7591	1			T1	2		T2	15		T3	3
valid_sources[0x2b]	8582	1			T1	6		T2	19		T3	3
valid_sources[0x2c]	7417	1			T1	1		T2	5		T3	19
valid_sources[0x2d]	7685	1			T1	10		T2	8		T3	9
valid_sources[0x2e]	8293	1			T1	2		T2	16		T3	21
valid_sources[0x2f]	8527	1			T1	3		T2	7		T3	9
valid_sources[0x30]	7009	1			T1	5		T2	3		T3	10
valid_sources[0x31]	11031	1			T1	4		T2	17		T3	5
valid_sources[0x32]	7407	1			T2	8		T3	2		T4	27
valid_sources[0x33]	8462	1			T1	6		T2	15		T3	4
valid_sources[0x34]	7580	1			T1	1		T2	5		T3	10
valid_sources[0x35]	7538	1			T1	1		T2	2		T3	3
valid_sources[0x36]	8488	1			T1	5		T2	16		T3	10
valid_sources[0x37]	9026	1			T1	2		T2	7		T3	7
valid_sources[0x38]	11781	1			T1	3		T2	19		T3	27
valid_sources[0x39]	9739	1			T1	4		T2	8		T3	12
valid_sources[0x3a]	7131	1			T1	2		T2	15		T3	21
valid_sources[0x3b]	11792	1			T1	1		T2	8		T4	47
valid_sources[0x3c]	7164	1			T1	1		T2	16		T4	34
valid_sources[0x3d]	14248	1			T1	5		T2	6		T3	9
valid_sources[0x3e]	9073	1			T1	7		T2	10		T3	20
valid_sources[0x3f]	7182	1			T1	11		T2	21		T3	8
valid_sources[0x40]	7930	1			T1	1		T2	12		T3	1
valid_sources[0x41]	15344	1			T1	2		T2	9		T3	6
valid_sources[0x42]	7438	1			T1	2		T2	8		T3	5
valid_sources[0x43]	7411	1			T1	7		T2	9		T3	4
valid_sources[0x44]	12408	1			T1	4		T2	9		T4	30
valid_sources[0x45]	13004	1			T1	8		T2	11		T3	8
valid_sources[0x46]	15955	1			T1	4		T2	8		T3	2
valid_sources[0x47]	8390	1			T1	1		T2	31		T3	9
valid_sources[0x48]	8322	1			T1	4		T2	8		T3	13
valid_sources[0x49]	10718	1			T1	9		T2	8		T3	6
valid_sources[0x4a]	14571	1			T1	6		T2	21		T3	1
valid_sources[0x4b]	20387	1			T1	6		T2	16		T4	29
valid_sources[0x4c]	7253	1			T1	3		T2	9		T4	26
valid_sources[0x4d]	7335	1			T1	3		T2	4		T3	10
valid_sources[0x4e]	10647	1			T1	6		T2	5		T3	1
valid_sources[0x4f]	7135	1			T1	5		T2	4		T4	29
valid_sources[0x50]	7533	1			T1	3		T2	5		T3	2
valid_sources[0x51]	7140	1			T1	4		T2	8		T3	23
valid_sources[0x52]	7332	1			T1	2		T2	10		T4	38
valid_sources[0x53]	10058	1			T1	6		T2	12		T3	6
valid_sources[0x54]	12427	1			T1	4		T2	14		T4	35
valid_sources[0x55]	15287	1			T2	10		T3	26		T4	28
valid_sources[0x56]	7775	1			T1	3		T2	10		T3	10
valid_sources[0x57]	9219	1			T1	3		T2	8		T3	5
valid_sources[0x58]	7852	1			T1	7		T2	8		T3	3
valid_sources[0x59]	12734	1			T1	7		T2	11		T3	7
valid_sources[0x5a]	7338	1			T1	4		T2	25		T4	35
valid_sources[0x5b]	7491	1			T1	12		T2	10		T3	1
valid_sources[0x5c]	7025	1			T1	5		T2	9		T3	3
valid_sources[0x5d]	7786	1			T1	5		T2	9		T3	5
valid_sources[0x5e]	14535	1			T1	4		T2	19		T3	8
valid_sources[0x5f]	7422	1			T1	4		T2	14		T3	6
valid_sources[0x60]	8137	1			T1	2		T2	13		T3	17
valid_sources[0x61]	12568	1			T1	4		T2	13		T4	19
valid_sources[0x62]	7332	1			T1	4		T2	10		T3	12
valid_sources[0x63]	7934	1			T1	3		T2	14		T3	6
valid_sources[0x64]	7185	1			T1	4		T2	2		T3	7
valid_sources[0x65]	10111	1			T1	3		T2	19		T3	8
valid_sources[0x66]	7599	1			T1	4		T2	8		T3	7
valid_sources[0x67]	15852	1			T1	1		T2	18		T3	6
valid_sources[0x68]	7500	1			T1	1		T2	11		T3	3
valid_sources[0x69]	11845	1			T1	2		T2	12		T3	6
valid_sources[0x6a]	8027	1			T1	6		T2	5		T3	4
valid_sources[0x6b]	7817	1			T1	7		T2	6		T3	15
valid_sources[0x6c]	6865	1			T1	5		T2	13		T3	8
valid_sources[0x6d]	7397	1			T1	2		T2	4		T3	21
valid_sources[0x6e]	7913	1			T1	4		T2	6		T3	7
valid_sources[0x6f]	7486	1			T1	2		T2	11		T3	6
valid_sources[0x70]	7194	1			T1	3		T2	16		T3	1
valid_sources[0x71]	11245	1			T1	1		T2	8		T3	8
valid_sources[0x72]	7566	1			T1	3		T2	11		T3	16
valid_sources[0x73]	8072	1			T1	2		T2	12		T4	33
valid_sources[0x74]	8475	1			T1	6		T2	16		T3	1
valid_sources[0x75]	7575	1			T1	5		T2	9		T3	4
valid_sources[0x76]	13363	1			T1	4		T2	4		T3	7
valid_sources[0x77]	12080	1			T2	12		T3	9		T4	26
valid_sources[0x78]	11669	1			T1	3		T2	15		T3	11
valid_sources[0x79]	10116	1			T1	7		T2	2		T3	14
valid_sources[0x7a]	7565	1			T1	2		T2	3		T3	4
valid_sources[0x7b]	7227	1			T1	9		T2	3		T3	6
valid_sources[0x7c]	7383	1			T1	6		T2	11		T3	4
valid_sources[0x7d]	6950	1			T1	4		T2	28		T3	3
valid_sources[0x7e]	8119	1			T1	4		T2	5		T3	3
valid_sources[0x7f]	6968	1			T1	2		T2	15		T3	12
valid_sources[0x80]	7432	1			T1	5		T2	24		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1027300

1

T1

435

T2

1259

T3

851

values[0x0]

all_enables

biggest_size

76590

1

T1

22

T2

103

T3

44

values[0x1]

all_enables

biggest_size

55503

1

T1

18

T2

56

T3

21