Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	25764	1			T1	8		T2	24		T3	8
auto[PWRUP]	95	1			T49	1		T13	1		T56	3
auto[ONEST_0]	65	1			T13	1		T57	2		T39	1
auto[ONEST_021]	11	1			T151	1		T212	1		T213	1
auto[ONEST_1]	79	1			T49	1		T13	1		T57	1
auto[ONEST_DONE]	2	1			T214	1		T215	1		-	-
auto[LP_0]	103	1			T13	2		T57	2		T56	1
auto[LP_021]	22	1			T49	1		T56	1		T44	1
auto[LP_1]	97	1			T56	1		T39	2		T47	2
auto[LP_EVAL]	59	1			T5	1		T49	1		T13	3
auto[LP_SLP]	418	1			T49	3		T13	7		T57	4
auto[LP_PWRUP]	17	1			T56	1		T44	1		T47	1
auto[NP_0]	139	1			T49	1		T13	2		T57	2
auto[NP_021]	28	1			T49	1		T56	1		T44	1
auto[NP_1]	123	1			T5	1		T13	1		T57	2
auto[NP_EVAL]	43	1			T49	1		T56	2		T47	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T154

1

T18

1

T216

1

min

25274

1

T1

8

T2

24

T3

8

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25281	1			T1	8		T2	24		T3	8
pow[0x1]	7	1			T217	1		T214	1		T218	1
pow[0x2]	20	1			T154	1		T16	2		T213	1
pow[0x3]	29	1			T13	1		T56	2		T47	1
pow[0x4]	55	1			T57	1		T39	1		T47	1
pow[0x5]	98	1			T5	1		T49	3		T13	1
pow[0x6]	235	1			T49	1		T13	1		T57	2
pow[0x7]	417	1			T5	1		T49	5		T13	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

177

1

T13

2

T56

3

T39

1

min

24906

1

T1

8

T2

24

T3

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	24906	1			T1	8		T2	24		T3	8
pow[0x1]	1	1			T219	1		-	-		-	-
pow[0x6]	1	1			T220	1		-	-		-	-
pow[0x8]	1	1			T13	1		-	-		-	-
pow[0x9]	9	1			T44	1		T47	1		T221	1
pow[0xa]	31	1			T56	1		T39	1		T222	1
pow[0xb]	26	1			T49	1		T57	1		T56	1
pow[0xc]	56	1			T49	1		T56	2		T39	1
pow[0xd]	120	1			T49	2		T57	1		T56	2
pow[0xe]	243	1			T49	1		T13	5		T56	4
pow[0xf]	502	1			T49	5		T13	6		T57	7