Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2094	1			T5	8		T49	11		T13	19
auto[PWRUP]	118	1			T49	3		T57	3		T56	2
auto[ONEST_0]	54	1			T49	1		T39	1		T44	1
auto[ONEST_021]	16	1			T49	1		T151	1		T48	1
auto[ONEST_1]	79	1			T5	1		T49	1		T56	1
auto[ONEST_DONE]	3	1			T327	1		T344	1		T345	1
auto[LP_0]	111	1			T49	1		T13	1		T56	1
auto[LP_021]	25	1			T44	1		T154	1		T16	1
auto[LP_1]	137	1			T5	1		T13	2		T56	4
auto[LP_EVAL]	59	1			T13	1		T56	1		T39	1
auto[LP_SLP]	473	1			T5	3		T49	1		T13	5
auto[LP_PWRUP]	26	1			T13	1		T15	1		T154	1
auto[NP_0]	219	1			T5	1		T49	2		T13	2
auto[NP_021]	44	1			T57	1		T56	1		T151	1
auto[NP_1]	217	1			T13	2		T57	1		T39	4
auto[NP_EVAL]	41	1			T13	1		T47	1		T15	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T13

1

T216

1

T346

1

min

1892

1

T5

9

T49

3

T13

12

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1899	1			T5	9		T49	4		T13	12
pow[0x1]	10	1			T48	1		T18	2		T347	1
pow[0x2]	27	1			T5	2		T13	1		T57	1
pow[0x3]	32	1			T39	1		T222	2		T154	2
pow[0x4]	45	1			T47	2		T151	1		T15	2
pow[0x5]	120	1			T49	1		T13	5		T57	2
pow[0x6]	219	1			T49	1		T13	2		T57	1
pow[0x7]	451	1			T5	2		T49	4		T13	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

155

1

T49

1

T57

3

T56

1

min

1347

1

T5

10

T49

1

T13

11

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1350	1			T5	10		T49	1		T13	11
pow[0x1]	12	1			T50	2		T348	1		T22	1
pow[0x2]	31	1			T50	2		T17	1		T149	1
pow[0x3]	39	1			T16	2		T52	3		T17	1
pow[0x4]	60	1			T48	4		T50	1		T15	2
pow[0x5]	2	1			T349	1		T350	1		-	-
pow[0x6]	3	1			T219	1		T351	1		T352	1
pow[0x7]	1	1			T219	1		-	-		-	-
pow[0x8]	2	1			T44	1		T347	1		-	-
pow[0x9]	9	1			T57	1		T39	1		T212	1
pow[0xa]	12	1			T56	1		T16	1		T213	1
pow[0xb]	28	1			T47	1		T213	1		T219	1
pow[0xc]	75	1			T49	1		T56	2		T47	3
pow[0xd]	121	1			T5	1		T13	2		T57	3
pow[0xe]	259	1			T13	1		T57	3		T56	3
pow[0xf]	518	1			T49	3		T13	6		T57	4