Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2606	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2888	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2726	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2714	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2578	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2440	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2538	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2757	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2702	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2728	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2631	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2649	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2734	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2817	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2744	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2723	0	0
adc_en_ctl_rd_A	2147483647	2237	0	0
adc_fsm_rst_rd_A	2147483647	2088	0	0
adc_intr_ctl_rd_A	2147483647	2845	0	0
adc_lp_sample_ctl_rd_A	2147483647	2114	0	0
adc_pd_ctl_rd_A	2147483647	2365	0	0
adc_sample_ctl_rd_A	2147483647	2166	0	0
adc_wakeup_ctl_rd_A	2147483647	2177	0	0
intr_enable_rd_A	2147483647	2835	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2606	0	0
T15	350160	29	0	0
T16	0	43	0	0
T17	0	6	0	0
T18	0	19	0	0
T19	0	9	0	0
T20	0	37	0	0
T21	0	34	0	0
T22	0	24	0	0
T23	0	22	0	0
T24	0	13	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2888	0	0
T15	350160	39	0	0
T16	0	29	0	0
T17	0	8	0	0
T18	0	21	0	0
T19	0	18	0	0
T20	0	42	0	0
T21	0	30	0	0
T22	0	21	0	0
T23	0	28	0	0
T24	0	14	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2726	0	0
T15	350160	49	0	0
T16	0	35	0	0
T17	0	6	0	0
T18	0	27	0	0
T19	0	18	0	0
T20	0	36	0	0
T21	0	46	0	0
T22	0	24	0	0
T23	0	25	0	0
T24	0	27	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2714	0	0
T15	350160	22	0	0
T16	0	33	0	0
T18	0	25	0	0
T19	0	14	0	0
T20	0	35	0	0
T21	0	49	0	0
T22	0	23	0	0
T23	0	12	0	0
T24	0	21	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0
T34	0	32	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2578	0	0
T15	350160	25	0	0
T16	0	16	0	0
T17	0	5	0	0
T18	0	23	0	0
T19	0	7	0	0
T20	0	46	0	0
T21	0	37	0	0
T22	0	17	0	0
T23	0	16	0	0
T24	0	9	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2440	0	0
T15	350160	38	0	0
T16	0	35	0	0
T17	0	9	0	0
T18	0	18	0	0
T19	0	19	0	0
T20	0	34	0	0
T21	0	38	0	0
T22	0	23	0	0
T23	0	27	0	0
T24	0	8	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2538	0	0
T15	350160	15	0	0
T16	0	32	0	0
T17	0	11	0	0
T18	0	12	0	0
T19	0	13	0	0
T20	0	31	0	0
T21	0	38	0	0
T22	0	19	0	0
T23	0	23	0	0
T24	0	14	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2757	0	0
T15	350160	42	0	0
T16	0	23	0	0
T17	0	9	0	0
T18	0	20	0	0
T19	0	7	0	0
T20	0	42	0	0
T21	0	47	0	0
T22	0	21	0	0
T23	0	34	0	0
T24	0	18	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2702	0	0
T15	350160	27	0	0
T16	0	51	0	0
T17	0	14	0	0
T18	0	31	0	0
T19	0	9	0	0
T20	0	39	0	0
T21	0	46	0	0
T23	0	17	0	0
T24	0	17	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0
T34	0	42	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2728	0	0
T15	350160	30	0	0
T16	0	18	0	0
T17	0	5	0	0
T18	0	19	0	0
T19	0	10	0	0
T20	0	40	0	0
T21	0	39	0	0
T22	0	29	0	0
T23	0	18	0	0
T24	0	8	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2631	0	0
T15	350160	39	0	0
T16	0	21	0	0
T17	0	10	0	0
T18	0	21	0	0
T19	0	8	0	0
T20	0	34	0	0
T21	0	38	0	0
T22	0	7	0	0
T23	0	27	0	0
T24	0	21	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2649	0	0
T15	350160	25	0	0
T16	0	20	0	0
T17	0	4	0	0
T18	0	12	0	0
T19	0	6	0	0
T20	0	66	0	0
T21	0	49	0	0
T22	0	12	0	0
T23	0	19	0	0
T24	0	13	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2734	0	0
T15	350160	23	0	0
T16	0	26	0	0
T17	0	10	0	0
T18	0	19	0	0
T19	0	8	0	0
T20	0	39	0	0
T21	0	38	0	0
T22	0	21	0	0
T23	0	5	0	0
T24	0	10	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2817	0	0
T15	350160	28	0	0
T16	0	30	0	0
T17	0	9	0	0
T18	0	16	0	0
T19	0	8	0	0
T20	0	24	0	0
T21	0	46	0	0
T22	0	21	0	0
T23	0	29	0	0
T24	0	24	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2744	0	0
T15	350160	24	0	0
T16	0	32	0	0
T17	0	1	0	0
T18	0	20	0	0
T19	0	18	0	0
T20	0	52	0	0
T21	0	36	0	0
T22	0	20	0	0
T23	0	20	0	0
T24	0	17	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2723	0	0
T15	350160	34	0	0
T16	0	31	0	0
T17	0	7	0	0
T18	0	16	0	0
T19	0	6	0	0
T20	0	37	0	0
T21	0	41	0	0
T22	0	13	0	0
T23	0	15	0	0
T24	0	15	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2237	0	0
T15	350160	20	0	0
T16	0	41	0	0
T17	0	3	0	0
T18	0	14	0	0
T19	0	17	0	0
T20	0	33	0	0
T21	0	34	0	0
T22	0	18	0	0
T23	0	20	0	0
T24	0	20	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2088	0	0
T15	350160	16	0	0
T16	0	24	0	0
T17	0	13	0	0
T18	0	15	0	0
T19	0	10	0	0
T20	0	41	0	0
T21	0	42	0	0
T22	0	6	0	0
T23	0	21	0	0
T24	0	7	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2845	0	0
T15	350160	34	0	0
T16	0	38	0	0
T17	0	10	0	0
T18	0	18	0	0
T19	0	14	0	0
T20	0	31	0	0
T21	0	46	0	0
T22	0	28	0	0
T23	0	26	0	0
T24	0	20	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2114	0	0
T15	350160	29	0	0
T16	0	23	0	0
T17	0	11	0	0
T18	0	12	0	0
T19	0	17	0	0
T20	0	33	0	0
T21	0	58	0	0
T22	0	18	0	0
T23	0	18	0	0
T24	0	21	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2365	0	0
T15	350160	27	0	0
T16	0	30	0	0
T17	0	13	0	0
T18	0	25	0	0
T19	0	8	0	0
T20	0	46	0	0
T21	0	38	0	0
T22	0	14	0	0
T23	0	28	0	0
T24	0	7	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2166	0	0
T15	350160	14	0	0
T16	0	40	0	0
T17	0	16	0	0
T18	0	17	0	0
T19	0	21	0	0
T20	0	35	0	0
T21	0	45	0	0
T22	0	22	0	0
T23	0	32	0	0
T24	0	22	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2177	0	0
T15	350160	34	0	0
T16	0	33	0	0
T17	0	8	0	0
T18	0	30	0	0
T19	0	18	0	0
T20	0	38	0	0
T21	0	21	0	0
T22	0	19	0	0
T23	0	41	0	0
T24	0	8	0	0
T25	443064	0	0	0
T26	258877	0	0	0
T27	161028	0	0	0
T28	249748	0	0	0
T29	161924	0	0	0
T30	160115	0	0	0
T31	228538	0	0	0
T32	754227	0	0	0
T33	183292	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2835	0	0
T15	0	45	0	0
T16	0	42	0	0
T17	0	21	0	0
T18	0	32	0	0
T19	0	18	0	0
T20	0	38	0	0
T35	186813	17	0	0
T36	0	26	0	0
T37	0	25	0	0
T38	0	14	0	0
T39	494689	0	0	0
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