Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1205676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1178691

1

T1

474

T2

911

T3

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2073610	1			T1	843		T2	1691		T15	1
values[0x0]	154908	1			T1	57		T2	90		T3	34
values[0x1]	155849	1			T1	52		T2	110		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	966583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1417784

1

T1

570

T2

1116

T3

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6662	1			T1	4		T2	2		T4	11
valid_sources[0x01]	6649	1			T2	9		T3	4		T4	12
valid_sources[0x02]	7028	1			T2	7		T3	15		T4	9
valid_sources[0x03]	15838	1			T1	1		T2	8		T4	13
valid_sources[0x04]	6912	1			T1	3		T2	7		T4	12
valid_sources[0x05]	6916	1			T2	5		T4	6		T5	57
valid_sources[0x06]	9664	1			T2	12		T4	11		T5	88
valid_sources[0x07]	10835	1			T1	9		T2	16		T4	13
valid_sources[0x08]	7064	1			T1	9		T2	1		T4	16
valid_sources[0x09]	7445	1			T2	6		T4	6		T5	85
valid_sources[0x0a]	6646	1			T2	7		T4	6		T5	67
valid_sources[0x0b]	15354	1			T2	9		T4	14		T5	83
valid_sources[0x0c]	8453	1			T1	16		T2	8		T4	12
valid_sources[0x0d]	6804	1			T1	1		T2	9		T4	11
valid_sources[0x0e]	9967	1			T1	6		T2	9		T4	12
valid_sources[0x0f]	7322	1			T2	13		T4	14		T5	7
valid_sources[0x10]	9679	1			T1	6		T2	9		T4	13
valid_sources[0x11]	11196	1			T2	4		T4	20		T5	90
valid_sources[0x12]	7605	1			T1	19		T2	11		T4	10
valid_sources[0x13]	11497	1			T1	13		T2	3		T4	12
valid_sources[0x14]	7334	1			T1	5		T2	6		T3	3
valid_sources[0x15]	11422	1			T1	1		T2	9		T4	7
valid_sources[0x16]	7922	1			T2	6		T4	7		T5	35
valid_sources[0x17]	14564	1			T1	7		T2	8		T4	8
valid_sources[0x18]	7882	1			T1	2		T2	6		T4	11
valid_sources[0x19]	7021	1			T2	6		T4	15		T5	30
valid_sources[0x1a]	7956	1			T2	12		T4	7		T5	40
valid_sources[0x1b]	11017	1			T2	13		T4	15		T5	82
valid_sources[0x1c]	7036	1			T2	9		T4	11		T5	43
valid_sources[0x1d]	8675	1			T2	9		T4	9		T5	65
valid_sources[0x1e]	11714	1			T1	5		T2	11		T4	5
valid_sources[0x1f]	11212	1			T1	2		T2	5		T4	8
valid_sources[0x20]	10159	1			T2	15		T4	10		T5	44
valid_sources[0x21]	9383	1			T2	8		T4	12		T5	30
valid_sources[0x22]	7134	1			T2	8		T4	9		T5	101
valid_sources[0x23]	6959	1			T2	8		T4	10		T5	44
valid_sources[0x24]	6737	1			T2	7		T4	6		T5	113
valid_sources[0x25]	7188	1			T1	7		T2	5		T4	9
valid_sources[0x26]	7061	1			T1	5		T2	14		T4	13
valid_sources[0x27]	11535	1			T2	6		T4	15		T5	39
valid_sources[0x28]	6906	1			T1	12		T2	5		T4	7
valid_sources[0x29]	10200	1			T1	9		T2	3		T4	18
valid_sources[0x2a]	7607	1			T2	3		T4	13		T5	32
valid_sources[0x2b]	10035	1			T1	2		T2	8		T4	8
valid_sources[0x2c]	7001	1			T1	2		T2	8		T4	5
valid_sources[0x2d]	7807	1			T1	1		T2	3		T4	12
valid_sources[0x2e]	8054	1			T1	5		T2	12		T4	12
valid_sources[0x2f]	6644	1			T1	2		T2	9		T4	11
valid_sources[0x30]	10654	1			T2	1		T4	15		T5	47
valid_sources[0x31]	9834	1			T2	23		T4	12		T5	41
valid_sources[0x32]	7011	1			T1	2		T2	10		T4	7
valid_sources[0x33]	11278	1			T1	1		T2	2		T4	12
valid_sources[0x34]	7204	1			T2	6		T4	14		T5	49
valid_sources[0x35]	20115	1			T2	11		T4	14		T5	37
valid_sources[0x36]	8843	1			T1	14		T2	10		T4	8
valid_sources[0x37]	7008	1			T2	5		T15	1		T4	10
valid_sources[0x38]	21937	1			T1	8		T2	4		T4	14
valid_sources[0x39]	7220	1			T2	6		T4	14		T5	109
valid_sources[0x3a]	7945	1			T1	13		T2	5		T4	10
valid_sources[0x3b]	7142	1			T1	5		T2	7		T15	1
valid_sources[0x3c]	6644	1			T1	2		T2	4		T4	10
valid_sources[0x3d]	7094	1			T2	5		T4	8		T5	92
valid_sources[0x3e]	9874	1			T1	2		T2	10		T4	18
valid_sources[0x3f]	7251	1			T1	4		T2	1		T4	3
valid_sources[0x40]	15826	1			T1	2		T2	7		T4	7
valid_sources[0x41]	12810	1			T1	10		T2	13		T4	6
valid_sources[0x42]	10124	1			T2	6		T4	11		T5	49
valid_sources[0x43]	12249	1			T2	5		T4	4		T5	25
valid_sources[0x44]	8036	1			T1	10		T2	7		T4	5
valid_sources[0x45]	6976	1			T2	11		T4	9		T5	51
valid_sources[0x46]	6513	1			T1	3		T4	14		T5	23
valid_sources[0x47]	6672	1			T1	5		T2	4		T4	15
valid_sources[0x48]	8703	1			T2	8		T4	9		T5	35
valid_sources[0x49]	12789	1			T3	8		T4	13		T5	23
valid_sources[0x4a]	7404	1			T2	7		T4	8		T5	49
valid_sources[0x4b]	7094	1			T1	5		T2	8		T4	12
valid_sources[0x4c]	7093	1			T2	7		T4	8		T5	18
valid_sources[0x4d]	7137	1			T1	4		T2	3		T4	15
valid_sources[0x4e]	7150	1			T1	1		T2	6		T4	13
valid_sources[0x4f]	7901	1			T2	5		T4	4		T5	11
valid_sources[0x50]	8614	1			T1	4		T2	6		T4	10
valid_sources[0x51]	11789	1			T2	7		T4	10		T5	54
valid_sources[0x52]	10964	1			T1	3		T2	5		T4	9
valid_sources[0x53]	12078	1			T1	4		T2	3		T4	8
valid_sources[0x54]	11292	1			T2	7		T4	4		T5	61
valid_sources[0x55]	11334	1			T2	9		T4	10		T5	36
valid_sources[0x56]	6502	1			T1	3		T2	3		T4	13
valid_sources[0x57]	7266	1			T2	2		T4	6		T5	43
valid_sources[0x58]	6826	1			T1	2		T2	1		T4	14
valid_sources[0x59]	7871	1			T2	4		T4	7		T5	72
valid_sources[0x5a]	8035	1			T2	3		T4	16		T5	42
valid_sources[0x5b]	6961	1			T1	3		T2	10		T4	3
valid_sources[0x5c]	6982	1			T1	1		T2	2		T15	1
valid_sources[0x5d]	11115	1			T2	4		T4	10		T5	19
valid_sources[0x5e]	13321	1			T1	1		T2	3		T4	13
valid_sources[0x5f]	8875	1			T1	4		T2	2		T4	5
valid_sources[0x60]	6394	1			T1	11		T2	3		T4	14
valid_sources[0x61]	6629	1			T2	5		T4	8		T5	12
valid_sources[0x62]	15461	1			T1	8		T2	14		T4	12
valid_sources[0x63]	8205	1			T2	13		T4	11		T5	120
valid_sources[0x64]	12343	1			T1	6		T2	4		T4	8
valid_sources[0x65]	6858	1			T1	3		T2	17		T4	14
valid_sources[0x66]	7644	1			T1	7		T3	1		T4	10
valid_sources[0x67]	7060	1			T2	4		T4	10		T5	47
valid_sources[0x68]	6803	1			T2	7		T4	10		T5	64
valid_sources[0x69]	7098	1			T2	12		T4	18		T5	111
valid_sources[0x6a]	9830	1			T2	2		T4	7		T5	47
valid_sources[0x6b]	19837	1			T1	3		T2	8		T4	4
valid_sources[0x6c]	7357	1			T2	12		T4	9		T5	42
valid_sources[0x6d]	6765	1			T1	18		T2	2		T4	7
valid_sources[0x6e]	7343	1			T2	11		T4	15		T5	25
valid_sources[0x6f]	7027	1			T1	11		T2	10		T4	2
valid_sources[0x70]	6787	1			T1	4		T2	8		T4	8
valid_sources[0x71]	6557	1			T1	1		T2	6		T4	8
valid_sources[0x72]	9973	1			T2	14		T4	14		T5	57
valid_sources[0x73]	10742	1			T2	4		T4	8		T5	32
valid_sources[0x74]	6653	1			T1	2		T2	4		T4	9
valid_sources[0x75]	6932	1			T1	5		T2	9		T4	8
valid_sources[0x76]	10773	1			T1	13		T2	11		T4	14
valid_sources[0x77]	17982	1			T1	8		T2	5		T4	7
valid_sources[0x78]	6842	1			T2	8		T15	1		T4	12
valid_sources[0x79]	7874	1			T1	16		T2	11		T4	10
valid_sources[0x7a]	9575	1			T1	3		T2	3		T4	10
valid_sources[0x7b]	11609	1			T1	13		T2	6		T3	10
valid_sources[0x7c]	12034	1			T1	5		T2	4		T4	9
valid_sources[0x7d]	6685	1			T1	3		T2	8		T4	4
valid_sources[0x7e]	6656	1			T1	1		T2	6		T4	11
valid_sources[0x7f]	12985	1			T1	7		T2	9		T4	13
valid_sources[0x80]	13030	1			T1	5		T2	4		T4	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1032474

1

T1

422

T2

822

T4

2472

values[0x0]

all_enables

biggest_size

84787

1

T1

33

T2

52

T3

18

values[0x1]

all_enables

biggest_size

61430

1

T1

19

T2

37

T3

11