Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30325	1			T1	9		T2	13		T4	15
auto[PWRUP]	136	1			T7	2		T33	2		T43	2
auto[ONEST_0]	78	1			T7	1		T33	1		T43	1
auto[ONEST_021]	23	1			T43	1		T169	1		T316	1
auto[ONEST_1]	97	1			T7	1		T43	2		T41	1
auto[ONEST_DONE]	4	1			T289	1		T317	1		T263	1
auto[LP_0]	158	1			T7	4		T11	1		T33	1
auto[LP_021]	39	1			T7	1		T41	1		T42	2
auto[LP_1]	137	1			T7	2		T33	2		T41	4
auto[LP_EVAL]	86	1			T7	2		T16	2		T34	1
auto[LP_SLP]	539	1			T7	6		T33	4		T16	4
auto[LP_PWRUP]	32	1			T16	1		T41	2		T318	1
auto[NP_0]	164	1			T7	2		T33	3		T16	2
auto[NP_021]	37	1			T16	1		T41	3		T42	1
auto[NP_1]	158	1			T7	3		T43	1		T34	1
auto[NP_EVAL]	49	1			T33	1		T41	1		T36	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T7

1

T41

1

T44

1

min

29754

1

T1

9

T2

13

T4

15

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29771	1			T1	9		T2	13		T4	15
pow[0x1]	4	1			T238	1		T319	1		T320	1
pow[0x2]	23	1			T43	1		T165	1		T44	2
pow[0x3]	43	1			T33	1		T43	1		T34	2
pow[0x4]	74	1			T7	2		T16	1		T41	4
pow[0x5]	150	1			T7	1		T41	4		T165	4
pow[0x6]	288	1			T7	4		T33	3		T16	2
pow[0x7]	575	1			T7	8		T33	4		T16	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

195

1

T33

2

T16

1

T34

1

min

29229

1

T1

9

T2

13

T4

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29229	1			T1	9		T2	13		T4	15
pow[0x3]	1	1			T7	1		-	-		-	-
pow[0x4]	2	1			T321	1		T322	1		-	-
pow[0x5]	1	1			T193	1		-	-		-	-
pow[0x6]	2	1			T323	1		T324	1		-	-
pow[0x7]	1	1			T325	1		-	-		-	-
pow[0x8]	5	1			T165	1		T326	1		T227	1
pow[0x9]	8	1			T316	1		T194	1		T323	1
pow[0xa]	22	1			T34	1		T318	1		T200	2
pow[0xb]	39	1			T41	1		T327	1		T328	1
pow[0xc]	72	1			T16	1		T41	3		T35	1
pow[0xd]	172	1			T33	2		T16	1		T43	2
pow[0xe]	327	1			T7	5		T11	1		T33	1
pow[0xf]	650	1			T7	12		T33	1		T16	3