Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2504	1			T7	22		T11	11		T27	10
auto[PWRUP]	153	1			T11	1		T33	1		T34	1
auto[ONEST_0]	91	1			T7	3		T34	1		T41	3
auto[ONEST_021]	24	1			T7	1		T44	1		T326	1
auto[ONEST_1]	96	1			T7	3		T16	1		T41	5
auto[ONEST_DONE]	6	1			T41	1		T238	1		T323	1
auto[LP_0]	166	1			T7	1		T33	1		T16	1
auto[LP_021]	40	1			T41	1		T42	1		T165	1
auto[LP_1]	166	1			T7	1		T33	1		T41	2
auto[LP_EVAL]	81	1			T11	1		T16	3		T43	1
auto[LP_SLP]	586	1			T7	10		T11	2		T33	6
auto[LP_PWRUP]	28	1			T7	1		T34	1		T42	1
auto[NP_0]	243	1			T11	2		T33	6		T16	2
auto[NP_021]	47	1			T11	1		T43	1		T34	1
auto[NP_1]	300	1			T7	6		T11	5		T33	4
auto[NP_EVAL]	30	1			T16	1		T43	1		T35	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T327

1

T329

1

T330

1

min

2158

1

T7

12

T11

21

T27

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2167	1			T7	12		T11	21		T27	10
pow[0x1]	14	1			T42	1		T165	1		T39	1
pow[0x2]	17	1			T33	1		T17	1		T169	1
pow[0x3]	45	1			T43	1		T41	3		T326	1
pow[0x4]	70	1			T16	1		T43	1		T34	1
pow[0x5]	167	1			T7	3		T16	1		T41	6
pow[0x6]	315	1			T7	7		T33	1		T16	1
pow[0x7]	593	1			T7	9		T11	2		T33	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

216

1

T7

4

T33

1

T43

1

min

1458

1

T7

3

T11

14

T27

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1460	1			T7	3		T11	14		T27	10
pow[0x1]	28	1			T33	2		T34	3		T37	2
pow[0x2]	27	1			T11	1		T33	1		T36	1
pow[0x3]	44	1			T11	2		T16	2		T34	1
pow[0x4]	66	1			T11	3		T33	3		T16	2
pow[0x5]	1	1			T23	1		-	-		-	-
pow[0x7]	2	1			T319	1		T331	1		-	-
pow[0x8]	4	1			T332	1		T333	1		T331	1
pow[0x9]	8	1			T7	1		T318	1		T334	1
pow[0xa]	29	1			T33	1		T41	1		T169	1
pow[0xb]	42	1			T43	1		T41	1		T165	1
pow[0xc]	95	1			T7	1		T43	2		T41	2
pow[0xd]	165	1			T7	1		T16	1		T43	2
pow[0xe]	322	1			T7	6		T11	1		T33	2
pow[0xf]	641	1			T7	9		T11	2		T33	6